dcm_dsgn.vhd

如何使用ISE和FPGA使用指南

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- FILL IN LIBRARY STATEMENTS HERE

entity dcm_dsgn is
    Port ( clk_33 : in std_logic;
           clk_25 : in std_logic;
           reset : in std_logic;
           dcm_reset : in std_logic;
           dcm_lock : out std_logic;
           din_clk33 : in std_logic;
           din_clk25 : in std_logic;
           dout_clk33 : out std_logic;
           dout_clk25 : out std_logic;
           pot_bist : in std_logic);
end dcm_dsgn;

architecture Behavioral of dcm_dsgn is

-- The following clocks are the output clocks from the DCMs
signal clk_33to25_dcm, clk_25_dcm : std_logic;

-- The following clocks are the output clocks from the BUFG and BUFGMUX
signal clk_33_buf, clk_25_buf : std_logic;

signal d0_clk33, d0_clk25, d1_clk33, d1_clk25 : std_logic;

-- FILL IN COMPONENT DECLARATIONS HERE

begin

-- DCM and BUFGMUX instantiations

-- FILL IN COMPONENT INSTANTIATIONS HERE

-- Dummy registers on each clock network

process (clk_33_buf, reset)
begin
  if (reset = '1') then
    d0_clk33 <= '0';
    d1_clk33 <= '0';
    dout_clk33 <= '0';
  elsif (clk_33_buf'event and clk_33_buf = '1') then
    d0_clk33 <= din_clk33;
    d1_clk33 <= d0_clk33;
    dout_clk33 <= d1_clk33;
  end if;
end process;

process (clk_25_buf, reset)
begin
  if (reset = '1') then
    d0_clk25 <= '0';
    d1_clk25 <= '0';
    dout_clk25 <= '0';
  elsif (clk_25_buf'event and clk_25_buf = '1') then
    d0_clk25 <= din_clk25;
    d1_clk25 <= d0_clk25;
    dout_clk25 <= d1_clk25;
  end if;
end process;

end Behavioral;