dcm_dsgn.v

如何使用ISE和FPGA使用指南

module dcm_dsgn (clk_33, clk_25, reset, dcm_reset, dcm_lock, din_clk33, din_clk25, 
                 dout_clk33, dout_clk25, pot_bist );

    input clk_33, clk_25;
    input reset, dcm_reset, pot_bist;
    input din_clk33, din_clk25;
    output dcm_lock;
    output dout_clk33, dout_clk25;
    reg dout_clk33, dout_clk25;

    // The following clocks are the output clocks from the DCMs
    wire clk_33to25_dcm, clk_25_dcm;

    // The following clocks are the output clocks from the BUFG and BUFGMUX
    wire clk_33_buf, clk_25_buf;
    
    reg d0_clk33, d0_clk25;
    reg d1_clk33, d1_clk25;

    // DCM & BUFGMUX instantiations:

// FILL IN COMPONENT INSTANTIATIONS HERE


// Dummy registers on each clock network
    always @ (posedge clk_33_buf, posedge reset)
    begin
	if (reset) begin
	      d0_clk33 <= 0;
		 d1_clk33	<= 0;
		 dout_clk33 <= 0;  end
	    else begin
	      d0_clk33 <= din_clk33;
		 d1_clk33 <= d0_clk33;
		 dout_clk33 <= d1_clk33;	end
    end // always @ (posedge clk_33_buf, posedge reset)
    
    always @ (posedge clk_25_buf, posedge reset)
    begin
	if (reset) begin
	      d0_clk25 <= 0;
		 d1_clk25	<= 0;
		 dout_clk25 <= 0; end
	    else begin
	      d0_clk25 <= din_clk25;
		 d1_clk25 <= d0_clk25;
		 dout_clk25 <= d1_clk25;	 end
    end // always @ (posedge clk_25_buf, posedge reset)
    
endmodule // dcm_dsgn