mac_ch.vhd

如何使用ISE和FPGA使用指南

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use work.correlate_and_accumulate_pack.all;

entity mac_ch is
    port (
        clk            : in  std_logic;
        reset          : in  std_logic;
        data_valid     : in  std_logic;
        dv_enable      : in  std_logic;
        data_ch        : in  std_logic_vector (7 downto 0);
        mac_data_valid : out std_logic;
        mac_data       : out std_logic_vector (20 downto 0));
end mac_ch;

architecture rtl of mac_ch is
    signal dv : std_logic_vector (3 downto 0);
    signal accumulator_cntr : std_logic_vector (7 downto 0);
    signal accumulator : std_logic_vector (20 downto 0);
    signal product : std_logic_vector(15 downto 0);
    signal data_ch_q0 : std_logic_vector (7 downto 0);
    signal data_valid_q0 : std_logic;
--    signal data_valid_l_q0 : std_logic;

    constant K : std_logic_vector (7 downto 0) := "11100010";  -- integer -30
    
begin  -- rtl

    mac_data_valid <= or_reduce(dv);

    process (clk)
    begin  -- process
        if rising_edge(clk) then
            if reset = '1' then
                data_ch_q0 <= (others => '0');
                accumulator <= (others => '0');
                mac_data <= (others => '0');
            else
                if dv_enable = '1' then
                    data_ch_q0 <= data_ch;
                end if;

                if data_valid_q0 = '1' and dv_enable = '1' then
--                if data_valid_l_q0 = '1' and dv_enable = '1' then
                    product <= K * data_ch_q0;
                    accumulator <= accumulator + product;
                    if accumulator_cntr = conv_std_logic_vector(255, 8) then
                        mac_data <= accumulator;
                        accumulator <= (others => '0');
                    end if;
                end if;
            end if;
        end if;
    end process;

    process (clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                dv <= (others => '0');
                data_valid_q0 <= '0';
--                data_valid_l_q0 <= '0';
            else
                if dv_enable = '1' then
                    data_valid_q0 <= data_valid;
--                    data_valid_l_q0 <= data_valid;
                    dv <= '0' & dv(3 downto 1);
                end if;
                if data_valid_q0 = '1' and dv_enable = '1' then
--                if data_valid_l_q0 = '1' and dv_enable = '1' then
                    if accumulator_cntr = conv_std_logic_vector(255, 8) then
                        dv(3) <= '1';
                    end if;
                end if;
            end if;
        end if;
    end process;

    process (clk)
    begin
        if rising_edge(clk) then
            if reset = '1' or accumulator_cntr = conv_std_logic_vector(255, 8) then
                accumulator_cntr <= (others => '0');
            else
                if data_valid_q0 = '1' and dv_enable = '1' then
--                if data_valid_l_q0 = '1' and dv_enable = '1' then
                    accumulator_cntr <= accumulator_cntr + 1;
                end if;
            end if;
        end if;
    end process;

end rtl;