data_control.vhd

如何使用ISE和FPGA使用指南

library ieee;
use ieee.std_logic_1164.all;

entity data_control is
    port (
        clk            : in  std_logic;
        reset          : in  std_logic;
        rd_data_cha    : in  std_logic_vector (7 downto 0);
        rd_data_chb    : in  std_logic_vector (7 downto 0);
        rd_data_chc    : in  std_logic_vector (7 downto 0);
        rd_data_chd    : in  std_logic_vector (7 downto 0);
        pn_lock_rd_clk : in  std_logic_vector(3 downto 0);
        almost_full    : in  std_logic_vector(3 downto 0);
        almost_empty   : in  std_logic_vector(3 downto 0);
        full           : in  std_logic_vector(3 downto 0);
        empty          : in  std_logic_vector(3 downto 0);
        rd             : out std_logic_vector (3 downto 0);
        valid_ch       : out std_logic_vector (3 downto 0);
        mac_dv         : out std_logic_vector (3 downto 0);
        final_data     : out std_logic_vector (7 downto 0);
        mac_cha        : out std_logic_vector (20 downto 0);
        mac_chb        : out std_logic_vector (20 downto 0);
        mac_chc        : out std_logic_vector (20 downto 0);
        mac_chd        : out std_logic_vector (20 downto 0));
end data_control;

architecture structure of data_control is

    component mac
        port (
            clk, reset, dv_enable                              : in  std_logic;
            data_valid                                         : in  std_logic_vector (3 downto 0);
            rd_data_cha, rd_data_chb, rd_data_chc, rd_data_chd : in  std_logic_vector (7 downto 0);
            mac_cha, mac_chb, mac_chc, mac_chd                 : out std_logic_vector (20 downto 0);
            mac_dv                                             : out std_logic_vector (3 downto 0));
    end component mac;

    component data_output_mux
        port (
            clk, reset, dv_enable                  : in  std_logic;
            data_valid                             : in  std_logic_vector (3 downto 0);
            data_cha, data_chb, data_chc, data_chd : in  std_logic_vector (7 downto 0);
            final_data                             : out std_logic_vector (7 downto 0);
            valid_ch                               : out std_logic_vector (3 downto 0));
    end component data_output_mux;

    component read_ch_arbiter
        port (
            clk, reset, waiting_cntr_en, next_ch_en : in  std_logic;
            almost_full, almost_empty, full, empty  : in  std_logic_vector (3 downto 0);
            pn_lock_rd_clk                          : in  std_logic_vector (3 downto 0);
            next_ch                                 : out std_logic_vector (3 downto 0));
    end component read_ch_arbiter;

    component data_control_fsm
        port (
            clk, reset                  : in  std_logic;
            next_ch                     : in  std_logic_vector (3 downto 0);
            rd                          : out std_logic_vector (3 downto 0);
            next_ch_en, waiting_cntr_en : out std_logic;
            data_valid                  : out std_logic_vector (3 downto 0);
            dv_enable                   : out std_logic);
    end component data_control_fsm;

    signal data_valid, next_ch                    : std_logic_vector (3 downto 0);
    signal waiting_cntr_en, next_ch_en, dv_enable : std_logic;

begin  -- structure

    mac_inst : mac
        port map(clk         => clk,
                 reset       => reset,
                 rd_data_cha => rd_data_cha,
                 rd_data_chb => rd_data_chb,
                 rd_data_chc => rd_data_chc,
                 rd_data_chd => rd_data_chd,
                 data_valid  => data_valid,
                 mac_cha     => mac_cha,
                 mac_chb     => mac_chb,
                 mac_chc     => mac_chc,
                 mac_chd     => mac_chd,
                 mac_dv      => mac_dv,
                 dv_enable   => dv_enable);

    data_output_mux_inst : data_output_mux
        port map(clk        => clk,
                 reset      => reset,
                 data_valid => data_valid,
                 data_cha   => rd_data_cha,
                 data_chb   => rd_data_chb,
                 data_chc   => rd_data_chc,
                 data_chd   => rd_data_chd,
                 final_data => final_data,
                 valid_ch   => valid_ch,
                 dv_enable  => dv_enable);

    read_ch_arbiter_inst : read_ch_arbiter
        port map(clk             => clk,
                 reset           => reset,
                 waiting_cntr_en => waiting_cntr_en,
                 next_ch_en      => next_ch_en,
                 pn_lock_rd_clk  => pn_lock_rd_clk,
                 almost_full     => almost_full,
                 almost_empty    => almost_empty,
                 full            => full,
                 empty           => empty,
                 next_ch         => next_ch);

    data_control_fsm_inst : data_control_fsm
        port map(clk             => clk,
                 reset           => reset,
                 rd              => rd,
                 waiting_cntr_en => waiting_cntr_en,
                 next_ch_en      => next_ch_en,
                 next_ch         => next_ch,
                 data_valid      => data_valid,
                 dv_enable       => dv_enable);


end structure;