data_control.srr

如何使用ISE和FPGA使用指南

#Build: Synplify Pro 8.8, Build 008R, Dec  7 2006
#install: Y:\XILI\Synplify_8_8\fpga_88
#OS: Windows 2000 5.0
#Hostname: SJC-XILISTG1

#Implementation: vhdl

#Fri Mar 16 10:05:14 2007

$ Start of Compile
#Fri Mar 16 10:05:14 2007

Synplicity VHDL Compiler, version 3.7, Build 110R, built Dec 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@N: CD720 :"Y:\XILI\Synplify_8_8\fpga_88\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@I:: "R:\training\desperf\labs\synthesis\synplify\vhdl\correlate_and_accumulate_pack.vhd"
@I:: "R:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd"
@I:: "R:\training\desperf\labs\synthesis\synplify\vhdl\read_ch_arbiter.vhd"
@I:: "R:\training\desperf\labs\synthesis\synplify\vhdl\mac.vhd"
@I:: "R:\training\desperf\labs\synthesis\synplify\vhdl\data_output_mux.vhd"
@I:: "R:\training\desperf\labs\synthesis\synplify\vhdl\data_control_fsm.vhd"
@I:: "R:\training\desperf\labs\synthesis\synplify\vhdl\data_control.vhd"
VHDL syntax check successful!
@N: CD630 :"R:\training\desperf\labs\synthesis\synplify\vhdl\data_control.vhd":6:7:6:18|Synthesizing work.data_control.structure 
@N: CD630 :"R:\training\desperf\labs\synthesis\synplify\vhdl\data_control_fsm.vhd":5:7:5:22|Synthesizing work.data_control_fsm.rtl 
@N: CD231 :"R:\training\desperf\labs\synthesis\synplify\vhdl\data_control_fsm.vhd":18:16:18:17|Using onehot encoding for type states (init="100000000000")
@W: CD604 :"R:\training\desperf\labs\synthesis\synplify\vhdl\data_control_fsm.vhd":74:12:74:25|OTHERS clause is not synthesized 
Post processing for work.data_control_fsm.rtl
@N: CD630 :"R:\training\desperf\labs\synthesis\synplify\vhdl\read_ch_arbiter.vhd":18:7:18:21|Synthesizing work.read_ch_arbiter.rtl 
Post processing for work.read_ch_arbiter.rtl
@N: CD630 :"R:\training\desperf\labs\synthesis\synplify\vhdl\data_output_mux.vhd":4:7:4:21|Synthesizing work.data_output_mux.rtl 
Post processing for work.data_output_mux.rtl
@N: CD630 :"R:\training\desperf\labs\synthesis\synplify\vhdl\mac.vhd":4:7:4:9|Synthesizing work.mac.structure 
@N: CD630 :"R:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":8:7:8:12|Synthesizing work.mac_ch.rtl 
Post processing for work.mac_ch.rtl
Post processing for work.mac.structure
Post processing for work.data_control.structure
@W: CL189 :"R:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":36:8:36:9|Register bit product(0) is always 0, optimizing ...
@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":36:8:36:9|Pruning Register bit <0> of product(15 downto 0)  
@W: CL189 :"R:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":36:8:36:9|Register bit accumulator(0) is always 0, optimizing ...
@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":36:8:36:9|Pruning Register bit <0> of accumulator(20 downto 0)  
@W: CL189 :"R:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":36:8:36:9|Register bit mac_data(0) is always 0, optimizing ...
@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":36:8:36:9|Pruning Register bit <0> of mac_data(20 downto 0)  
@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":36:8:36:9|Pruning Register bit <15> of product(15 downto 1)  
@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":36:8:36:9|Pruning Register bit <14> of product(15 downto 1)  
@N: CL201 :"R:\training\desperf\labs\synthesis\synplify\vhdl\data_control_fsm.vhd":28:8:28:9|Trying to extract state machine for register cs
Extracted state machine for register cs
State machine has 12 reachable states with original encodings of:
   000000000001
   000000000010
   000000000100
   000000001000
   000000010000
   000000100000
   000001000000
   000010000000
   000100000000
   001000000000
   010000000000
   100000000000
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Mar 16 10:05:15 2007

###########################################################]
Synplicity Xilinx Technology Mapper, Version 8.8.0, Build 386R, Built Dec 15 2006 20:49:13
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8
Reading constraint file: R:\training\desperf\labs\synthesis\synplify\vhdl\data_control.sdc
Reading constraint file: R:\training\desperf\labs\synthesis\synplify\vhdl\data_control_fsm.sdc
@N|Using encoding styles selected by FSM Explorer.
Data created on Tue Nov 08 15:30:36 2005
@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
Adding property syn_encoding in cell data_control_fsm, value "onehot", to instance data_control_fsm_inst.cs[0:11]
Reading Xilinx I/O pad type table from file <Y:\XILI\Synplify_8_8\fpga_88\lib/xilinx/x_io_tbl.txt> 
Reading Xilinx Rocket I/O parameter type table from file <Y:\XILI\Synplify_8_8\fpga_88\lib/xilinx/gttype.txt> 


Automatic dissolve at startup in view:work.mac(structure) of mac_chd_inst(mac_ch)
Automatic dissolve at startup in view:work.mac(structure) of mac_chc_inst(mac_ch)
Automatic dissolve at startup in view:work.mac(structure) of mac_chb_inst(mac_ch)
Automatic dissolve at startup in view:work.mac(structure) of mac_cha_inst(mac_ch)
Automatic dissolve at startup in view:work.data_control(structure) of data_output_mux_inst(data_output_mux)
Automatic dissolve at startup in view:work.data_control(structure) of mac_inst(mac)
@N: MT206 |Autoconstrain Mode is ON
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 46MB peak: 47MB)
@N:"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Found counter in view:work.data_control(structure) inst mac_inst.mac_chd_inst.accumulator_cntr[7:0]
@N:"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Found counter in view:work.data_control(structure) inst mac_inst.mac_chc_inst.accumulator_cntr[7:0]
@N:"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Found counter in view:work.data_control(structure) inst mac_inst.mac_chb_inst.accumulator_cntr[7:0]
@N:"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Found counter in view:work.data_control(structure) inst mac_inst.mac_cha_inst.accumulator_cntr[7:0]
Encoding state machine work.data_control_fsm(rtl)-cs[0:11]
original code -> new code
   000000000001 -> 000000000001
   000000000010 -> 000000000010
   000000000100 -> 000000000100
   000000001000 -> 000000001000
   000000010000 -> 000000010000
   000000100000 -> 000000100000
   000001000000 -> 000001000000
   000010000000 -> 000010000000
   000100000000 -> 000100000000
   001000000000 -> 001000000000
   010000000000 -> 010000000000
   100000000000 -> 100000000000
@W: BN116 :"r:\training\desperf\labs\synthesis\synplify\vhdl\data_control_fsm.vhd":72:12:72:27|Removing sequential instance cs[0] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"r:\training\desperf\labs\synthesis\synplify\vhdl\data_control_fsm.vhd":46:12:46:23|Removing sequential instance cs[11] of view:PrimLib.dff(prim) because there are no references to its outputs 

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 47MB)


######### START OF GENERATED CLOCK OPTIMIZATION REPORT #########[

================================================================
		Instance:Pin		Generated Clock Optimization Status
================================================================


######### END OF GENERATED CLOCK OPTIMIZATION REPORT #########]


Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 47MB)

Clock Buffers:
  Inserting Clock buffer for port clk,	TNM=clk


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 48MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 49MB)

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 49MB peak: 50MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		     0.00ns		 192 /       192
   2		0h:00m:01s		     0.00ns		 192 /       192
   3		0h:00m:01s		     0.00ns		 192 /       192
------------------------------------------------------------

Timing driven replication report
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[0]" with 5 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chb_inst.accumulator_cntr[0]" with 5 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[0]" with 5 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[0]" with 5 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[7]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[6]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chb_inst.accumulator_cntr[7]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[7]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[6]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[7]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[6]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chb_inst.accumulator_cntr[6]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[4]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[1]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[2]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[3]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[4]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[1]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[2]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[3]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[1]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\vhdl\mac_ch.vhd":84:8:84:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[5]" with 4 loads has been replicated 1 time(s) to improve timing