data_control_fsm.vhd

如何使用ISE和FPGA使用指南

library ieee;
use ieee.std_logic_1164.all;

entity data_control_fsm is
    port (
        clk             : in  std_logic;
        reset           : in  std_logic;
        next_ch         : in  std_logic_vector (3 downto 0);
        rd              : out std_logic_vector (3 downto 0);
        next_ch_en      : out std_logic;
        waiting_cntr_en : out std_logic;
        data_valid      : out std_logic_vector (3 downto 0);
        dv_enable       : out std_logic);
end data_control_fsm;

architecture rtl of data_control_fsm is
    type states is (init, waiting, st_rd_cha, st_rd_chb, st_rd_chc, st_rd_chd, wait_st1, wait_st2, wait_st3, wait_st4, wait_st5, wait_st6);
    signal cs, ns : states;
    signal dv_enable_i : std_logic;
begin  -- rtl

    dv_enable <= dv_enable_i;
    dv_enable_i <= '1' when (cs = st_rd_cha or cs = st_rd_chb or cs = st_rd_chc or cs = st_rd_chd) else '0';

    process (clk)
    begin  -- process
        if rising_edge(clk) then
            if reset = '1' then
                cs <= init;
                data_valid <= (others => '0');
            else
                cs <= ns;
                if dv_enable_i = '1' then
                    data_valid <= next_ch;
                end if;
            end if;
        end if;
    end process;

    data_control_fsm: process (cs, next_ch)
    begin  -- process
        -- defaults
        ns <= cs;
        case cs is
            when init =>
                ns <= waiting;
            when waiting =>
                case next_ch is
                    when "0001" =>
                        ns <= st_rd_cha;
                    when "0010" =>
                        ns <= st_rd_chb;
                    when "0100" =>
                        ns <= st_rd_chc;
                    when "1000" =>
                        ns <= st_rd_chd;
                    when others => null;
                end case;
            when st_rd_cha | st_rd_chb | st_rd_chc | st_rd_chd =>
                ns <= wait_st1;
            when wait_st1 =>
                ns <= wait_st2;
            when wait_st2 =>
                ns <= wait_st3;
            when wait_st3 =>
                ns <= wait_st4;
            when wait_st4 =>
                ns <= wait_st5;
            when wait_st5 =>
                ns <= wait_st6;
            when wait_st6 =>
                ns <= waiting;
            when others =>
                ns <= init;
        end case;
    end process;

    ---------------------------------------------------------------------------
    -- Output Decoding
    ---------------------------------------------------------------------------
    -- clock enables for read_ch_arbiter
    process (clk)
    begin  -- process
        if rising_edge(clk) then
            if reset = '1' then
                next_ch_en <= '0';
                waiting_cntr_en <= '0';
            else
                -- defaults
                waiting_cntr_en <= '0';
                next_ch_en <= '0';
                if ns = st_rd_cha or ns = st_rd_chb or ns = st_rd_chc or ns = st_rd_chd then
                    waiting_cntr_en <= '1';
                end if;
                if ns = wait_st5 or (ns = waiting and cs = waiting) then
                    next_ch_en <= '1';
                end if;
            end if;
        end if;
    end process;

    -- rd decoding
    rd(0) <= '1' when cs = st_rd_cha else '0';
    rd(1) <= '1' when cs = st_rd_chb else '0';
    rd(2) <= '1' when cs = st_rd_chc else '0';
    rd(3) <= '1' when cs = st_rd_chd else '0';
    
end rtl;