data_control.srr

如何使用ISE和FPGA使用指南

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		     0.00ns		 192 /       192
   2		0h:00m:01s		     0.00ns		 192 /       192
   3		0h:00m:01s		     0.00ns		 192 /       192
------------------------------------------------------------

Timing driven replication report
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chb_inst.accumulator_cntr[0]" with 5 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[0]" with 5 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[0]" with 5 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[0]" with 5 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[7]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[6]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chb_inst.accumulator_cntr[7]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[7]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[6]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[6]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[7]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chb_inst.accumulator_cntr[6]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[4]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[2]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[3]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[4]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[5]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[2]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[3]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[1]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[5]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chd_inst.accumulator_cntr[1]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[4]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[5]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chb_inst.accumulator_cntr[1]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chb_inst.accumulator_cntr[2]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chb_inst.accumulator_cntr[3]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chb_inst.accumulator_cntr[4]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chb_inst.accumulator_cntr[5]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_chc_inst.accumulator_cntr[1]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[3]" with 4 loads has been replicated 1 time(s) to improve timing 
@N: FX271 :"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Instance "mac_inst.mac_cha_inst.accumulator_cntr[2]" with 4 loads has been replicated 1 time(s) to improve timing 
Added 32 Registers via timing driven replication
Added 4 LUTs via timing driven replication

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:03s		    -0.02ns		 216 /       224
   2		0h:00m:03s		    -0.02ns		 216 /       224
   3		0h:00m:04s		    -0.02ns		 216 /       224
Timing driven replication report
No replication required.

   4		0h:00m:04s		    -0.02ns		 216 /       224
   5		0h:00m:04s		    -0.02ns		 216 /       224
   6		0h:00m:04s		    -0.02ns		 216 /       224
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:04s		    -0.87ns		 216 /       224
   2		0h:00m:04s		    -0.87ns		 216 /       224
   3		0h:00m:05s		    -0.87ns		 216 /       224
Timing driven replication report
No replication required.

   4		0h:00m:05s		    -0.87ns		 216 /       224
   5		0h:00m:05s		    -0.87ns		 216 /       224
   6		0h:00m:05s		    -0.87ns		 216 /       224
------------------------------------------------------------

Net buffering Report for view:work.data_control(verilog):
No nets needed buffering.


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:05s; Memory used current: 49MB peak: 50MB)
@N: FX164 |The option to pack flops in the IOB has not been specified 

Finished restoring hierarchy (Time elapsed 0h:00m:05s; Memory used current: 49MB peak: 50MB)
Writing Analyst data base R:\training\desperf\labs\synthesis\synplify\verilog\data_control.srm
@N: BN225 |Writing default property annotation file R:\training\desperf\labs\synthesis\synplify\verilog\data_control.map.
Writing EDIF Netlist and constraint files
Reading Xilinx net attributes from file <Y:\XILI\Synplify_8_8\fpga_88\lib/xilinx/netattr.txt> 
Version 8.8
Found clock data_control|clk with period 2.47ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Mar 16 10:45:45 2007
#


Top view:               data_control
Requested Frequency:    405.5 MHz
Wire load mode:         top
Paths requested:        0
Constraint File(s):    R:\training\desperf\labs\synthesis\synplify\verilog\data_control.sdc
                       R:\training\desperf\labs\synthesis\synplify\verilog\data_control_fsm.sdc
                       
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: -0.435

                     Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock       Frequency     Frequency     Period        Period        Slack      Type         Group                
--------------------------------------------------------------------------------------------------------------------------
data_control|clk     405.5 MHz     344.6 MHz     2.466         2.902         -0.435     inferred     Autoconstr_clkgroup_0
==========================================================================================================================





Clock Relationships
*******************

Clocks                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------
Starting          Ending            |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------
data_control|clk  data_control|clk  |  2.466       -0.435  |  No paths    -      |  No paths    -      |  No paths    -    
===========================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report for data_control 

Mapping to part: xc4vlx15sf363-12
Cell usage:
DSP48           4 uses
FDR             36 uses
FDRE            188 uses
GND             5 uses
MUXCY_L         24 uses
MUXF5           4 uses
VCC             5 uses
XORCY           28 uses
LUT1            40 uses
LUT2            36 uses
LUT3            52 uses
LUT4            88 uses

I/O ports: 158
I/O primitives: 157
IBUF           53 uses
OBUF           104 uses

BUFGP          1 use

I/O Register bits:                  0
Register bits not including I/Os:   224 (1%)

DSP48s: 4 of 32 (12%)

Global Clock Buffers: 1 of 32 (3%)

Total load per clock:
   data_control|clk: 228

Mapping Summary:
Total  LUTs: 216 (1%)

Mapper successful!
Process took 0h:00m:07s realtime, 0h:00m:06s cputime
# Fri Mar 16 10:45:46 2007

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