data_control.srr

如何使用ISE和FPGA使用指南

#Build: Synplify Pro 8.8, Build 008R, Dec  7 2006
#install: Y:\XILI\Synplify_8_8\fpga_88
#OS: Windows 2000 5.0
#Hostname: SJC-XILISTG1

#Implementation: verilog

#Fri Mar 16 10:45:36 2007

$ Start of Compile
#Fri Mar 16 10:45:36 2007

Synplicity Verilog Compiler, version 3.7, Build 110R, built Dec 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"Y:\XILI\Synplify_8_8\fpga_88\lib\xilinx\unisim.v"
@I::"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v"
@I::"R:\training\desperf\labs\synthesis\synplify\verilog\read_ch_arbiter.v"
@I::"R:\training\desperf\labs\synthesis\synplify\verilog\mac.v"
@I::"R:\training\desperf\labs\synthesis\synplify\verilog\data_output_mux.v"
@I::"R:\training\desperf\labs\synthesis\synplify\verilog\data_control_fsm.v"
@I::"R:\training\desperf\labs\synthesis\synplify\verilog\data_control.v"
Verilog syntax check successful!
Selecting top level module data_control
@N: CG364 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":2:7:2:12|Synthesizing module mac_ch

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <31> of product_7[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <30> of product_7[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <29> of product_7[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <28> of product_7[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <27> of product_7[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <26> of product_7[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <25> of product_7[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <24> of product_7[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <23> of product_7[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <22> of product_7[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <21> of product_7[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <31> of accumulator_11[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <30> of accumulator_11[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <29> of accumulator_11[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <28> of accumulator_11[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <27> of accumulator_11[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <26> of accumulator_11[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <25> of accumulator_11[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <24> of accumulator_11[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <23> of accumulator_11[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <22> of accumulator_11[31:0] - not in use ...

@W: CL170 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning bit <21> of accumulator_11[31:0] - not in use ...

@N: CG364 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac.v":2:7:2:9|Synthesizing module mac

@N: CG364 :"R:\training\desperf\labs\synthesis\synplify\verilog\data_output_mux.v":2:7:2:21|Synthesizing module data_output_mux

@N: CG364 :"R:\training\desperf\labs\synthesis\synplify\verilog\read_ch_arbiter.v":14:7:14:21|Synthesizing module read_ch_arbiter

@W: CL169 :"R:\training\desperf\labs\synthesis\synplify\verilog\read_ch_arbiter.v":73:4:73:9|Pruning Register priority_v[3:0] 

@N: CG364 :"R:\training\desperf\labs\synthesis\synplify\verilog\data_control_fsm.v":7:7:7:22|Synthesizing module data_control_fsm

@W: CL169 :"R:\training\desperf\labs\synthesis\synplify\verilog\data_control_fsm.v":103:4:103:9|Pruning Register prev_ch[3:0] 

@N: CG364 :"R:\training\desperf\labs\synthesis\synplify\verilog\data_control.v":2:7:2:18|Synthesizing module data_control

@N: CL201 :"R:\training\desperf\labs\synthesis\synplify\verilog\data_control_fsm.v":37:4:37:9|Trying to extract state machine for register cs
Extracted state machine for register cs
State machine has 12 reachable states with original encodings of:
   000000000001
   000000000010
   000000000100
   000000001000
   000000010000
   000000100000
   000001000000
   000010000000
   000100000000
   001000000000
   010000000000
   100000000000
@W: CL189 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Register bit product[0] is always 0, optimizing ...
@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning Register bit <0> of product[20:0] 

@W: CL189 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Register bit accumulator[0] is always 0, optimizing ...
@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning Register bit <0> of accumulator[20:0] 

@W: CL189 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Register bit mac_data[0] is always 0, optimizing ...
@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning Register bit <0> of mac_data[20:0] 

@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning Register bit <20> of product[20:1] 

@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning Register bit <19> of product[20:1] 

@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning Register bit <18> of product[20:1] 

@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning Register bit <17> of product[20:1] 

@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning Register bit <16> of product[20:1] 

@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning Register bit <15> of product[20:1] 

@W: CL171 :"R:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":23:4:23:9|Pruning Register bit <14> of product[20:1] 

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Mar 16 10:45:37 2007

###########################################################]
Synplicity Xilinx Technology Mapper, Version 8.8.0, Build 386R, Built Dec 15 2006 20:49:13
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8
Reading constraint file: R:\training\desperf\labs\synthesis\synplify\verilog\data_control.sdc
Reading constraint file: R:\training\desperf\labs\synthesis\synplify\verilog\data_control_fsm.sdc
@N|Using encoding styles selected by FSM Explorer.
Data created on Wed Nov 09 16:42:18 2005
@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
Adding property syn_encoding in cell data_control_fsm, value "onehot", to instance data_control_fsm_inst.cs[11:0]
Reading Xilinx I/O pad type table from file <Y:\XILI\Synplify_8_8\fpga_88\lib/xilinx/x_io_tbl.txt> 
Reading Xilinx Rocket I/O parameter type table from file <Y:\XILI\Synplify_8_8\fpga_88\lib/xilinx/gttype.txt> 


Automatic dissolve at startup in view:work.mac(verilog) of mac_chd_inst(mac_ch)
Automatic dissolve at startup in view:work.mac(verilog) of mac_chc_inst(mac_ch)
Automatic dissolve at startup in view:work.mac(verilog) of mac_chb_inst(mac_ch)
Automatic dissolve at startup in view:work.mac(verilog) of mac_cha_inst(mac_ch)
Automatic dissolve at startup in view:work.data_control(verilog) of data_output_mux_inst(data_output_mux)
Automatic dissolve at startup in view:work.data_control(verilog) of mac_inst(mac)
@N: MT206 |Autoconstrain Mode is ON
RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 46MB peak: 47MB)
@N:"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Found counter in view:work.data_control(verilog) inst mac_inst.mac_chd_inst.accumulator_cntr[7:0]
@N:"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Found counter in view:work.data_control(verilog) inst mac_inst.mac_chc_inst.accumulator_cntr[7:0]
@N:"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Found counter in view:work.data_control(verilog) inst mac_inst.mac_chb_inst.accumulator_cntr[7:0]
@N:"r:\training\desperf\labs\synthesis\synplify\verilog\mac_ch.v":76:4:76:9|Found counter in view:work.data_control(verilog) inst mac_inst.mac_cha_inst.accumulator_cntr[7:0]
Encoding state machine work.data_control_fsm(verilog)-cs[11:0]
original code -> new code
   000000000001 -> 000000000001
   000000000010 -> 000000000010
   000000000100 -> 000000000100
   000000001000 -> 000000001000
   000000010000 -> 000000010000
   000000100000 -> 000000100000
   000001000000 -> 000001000000
   000010000000 -> 000010000000
   000100000000 -> 000100000000
   001000000000 -> 001000000000
   010000000000 -> 010000000000
   100000000000 -> 100000000000
@W: BN116 :"r:\training\desperf\labs\synthesis\synplify\verilog\data_control_fsm.v":91:5:91:12|Removing sequential instance cs[11] of view:PrimLib.dff(prim) because there are no references to its outputs 
@W: BN116 :"r:\training\desperf\labs\synthesis\synplify\verilog\data_control_fsm.v":60:5:60:8|Removing sequential instance cs[0] of view:PrimLib.dff(prim) because there are no references to its outputs 

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 47MB)


######### START OF GENERATED CLOCK OPTIMIZATION REPORT #########[

================================================================
		Instance:Pin		Generated Clock Optimization Status
================================================================


######### END OF GENERATED CLOCK OPTIMIZATION REPORT #########]


Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 46MB peak: 47MB)

Clock Buffers:
  Inserting Clock buffer for port clk,	TNM=clk


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 48MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 49MB)

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 48MB peak: 50MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------