mac_ch.v

来自「如何使用ISE和FPGA使用指南」· Verilog 代码 · 共 96 行

module mac_ch (input clk, 
	       input reset, 
	       input data_valid, 
	       input dv_enable, 
	       input [7:0] data_ch, 
	       output reg [20:0] mac_data, 
	       output mac_data_valid);

    reg [3:0] 	  dv;
    reg [7:0]  accumulator_cntr;
    integer    product;
    integer    accumulator;
    reg signed [7:0] data_ch_q0;
    
    reg       data_valid_q0;
//  reg 	    data_valid_l_q0;

    parameter K = -30;

    assign    mac_data_valid = | dv; // hold for four clock cycles (multi-cycle output path)
        
    always @ (posedge clk)
    begin
	if (reset)
	begin
	    data_ch_q0 <= 0;
	    accumulator <= 0;
	    mac_data <= 0;
	end // if (reset)
	else
	begin
	    // defaults
	    if (dv_enable)
	      data_ch_q0 <= data_ch;
		
	    if (data_valid_q0 & dv_enable)
//	      if (data_valid_l_q0 & dv_enable)
	    begin
		product <= K * data_ch_q0; 
		accumulator <= accumulator + product;
		
		if (accumulator_cntr == 255)
		begin
		    mac_data <= accumulator;
		    accumulator <= 0;
		end // if (accumulator_cntr == 255)
	    end // if (data_valid_q0)
		
	end // else: !if(reset)
    end // always @ (posedge clk)

    always @ (posedge clk)
    begin
	if (reset)
	begin
	    dv <= 0;
	    data_valid_q0 <= 0;
//	      data_valid_l_q0 <= 0;
	end // if (reset)
	else
	begin
	    if (dv_enable)
	    begin 
		data_valid_q0 <= data_valid;
//		  data_valid_l_q0 <= data_valid;
		dv <= {1'b0, dv[3:1]};
	    end // if (dv_enable)
	    if (data_valid_q0 & dv_enable)
//	      if (data_valid_l_q0 & dv_enable)
	      if (accumulator_cntr == 255)
		dv[3] <= 1;
	end // else: !if(reset)
    end // always @ (posedge clk)

    always @ (posedge clk)
    begin
	if (reset | accumulator_cntr == 255)
	  accumulator_cntr <= 0;
	else
	  if (data_valid_q0 & dv_enable)
//	      if (data_valid_l_q0 & dv_enable)
	      accumulator_cntr <= accumulator_cntr + 1;
    end // always @ (posedge clk)
    
endmodule // mac_ch