data_control_fsm.v

如何使用ISE和FPGA使用指南

//_____________________________________________________________________________________
// This state machine creates the read enable for the channel FIFOs.  It also creates the
// output multiplexing controls and the controls for the MAC for each channel seperately.
//_____________________________________________________________________________________

module data_control_fsm(input clk, 
			input reset,
			input [3:0] next_ch,
			output dv_enable,
			output [3:0] rd, 
			output reg waiting_cntr_en, 
			output reg next_ch_en, 
			output reg [3:0] data_valid);
    
    //_____________________________________________________________________________________
    // Internal signals
    reg [11:0] 	  ns,cs;
	reg [3:0] prev_ch;
    //_____________________________________________________________________________________
    
    parameter init = 12'h001,
	      waiting = 12'h002,
	      st_rd_cha = 12'h004,
	      st_rd_chb = 12'h008,
	      st_rd_chc = 12'h010,
	      st_rd_chd = 12'h020,
	      wait_st1 = 12'h040,
	      wait_st2 = 12'h080,
	      wait_st3 = 12'h100,
	      wait_st4 = 12'h200,
	      wait_st5 = 12'h400,
	      wait_st6 = 12'h800;

    assign    dv_enable = (cs == st_rd_cha) | (cs == st_rd_chb) | (cs == st_rd_chc) | (cs == st_rd_chd);
    
    always @ (posedge clk)
      if (reset)
	begin
	    cs <= init;
	    data_valid <= 0;
	end
      else 
      begin
	  cs <= ns;
	  if (dv_enable)
	    data_valid <= next_ch;
      end // else: !if(reset)
    
    
    //_____________________________________________________________________________________
    // State Decoding
    //_____________________________________________________________________________________
    always @ (cs or next_ch)
    begin : data_control_fsm
	// defaults
	ns = cs;
	
	case (cs)
	    init:
	      ns = waiting;
	    waiting:
	      case (next_ch)
		  4'b0001:
		    ns = st_rd_cha;
		  4'b0010:
		    ns = st_rd_chb;
		  4'b0100:
		    ns = st_rd_chc;
		  4'b1000:
		    ns = st_rd_chd;
	      endcase // case(next_ch)
	    st_rd_cha:
	      ns = wait_st1;
	    st_rd_chb:
	      ns = wait_st1;
	    st_rd_chc:
	      ns = wait_st1;
	    st_rd_chd:
	      ns = wait_st1;
	    wait_st1:
	      ns = wait_st2;
	    wait_st2:
	      ns = wait_st3;
	    wait_st3:
	      ns = wait_st4;
	    wait_st4:
	      ns = wait_st5;
	    wait_st5:
	      ns = wait_st6;
	    wait_st6:
	      ns = waiting;
	    default:
	      ns = init;
	endcase // case(cs)
    end // block: data_control_fsm
    
    //_____________________________________________________________________________________
    // Output Decoding
    //_____________________________________________________________________________________
    
    // clock enables for read_ch_arbiter
    always @ (posedge clk)
    begin
        if (reset)
        begin
	    next_ch_en <= 0;
	    waiting_cntr_en <= 0;
	end
   	else
	begin
 	    prev_ch = {(ns == st_rd_chd), (ns == st_rd_chc), (ns == st_rd_chb), (ns == st_rd_cha)};
	    waiting_cntr_en <= |prev_ch;
	    // default
	    next_ch_en <= 0;
	    if (ns == wait_st5 | (ns == waiting & cs == waiting))
	        next_ch_en <= 1;
	end
    end	    

    //_____________________________________________________________________________________
    // rd decoding
    //_____________________________________________________________________________________
    assign rd = {(cs == st_rd_chd), (cs == st_rd_chc), (cs == st_rd_chb), (cs == st_rd_cha)};
    
endmodule // data_control_fsm