data_output_mux.v

如何使用ISE和FPGA使用指南

module data_output_mux(input clk, 
		       input reset, 
		       input dv_enable,
		       input [3:0] data_valid, 
		       input [7:0] data_cha, 
		       input [7:0] data_chb, 
		       input [7:0] data_chc, 
		       input [7:0] data_chd, 
		       output reg [7:0] final_data, 
		       output [3:0] valid_ch);
    
    reg [3:0] 	 v_ch [3:0];
    integer 	 i;

    assign 	 valid_ch = v_ch[3] | v_ch[2] | v_ch[1] | v_ch[0];
    
    always @ (posedge clk)
    begin
	if (reset)
	begin
	    for (i = 0; i <= 3; i = i + 1)
	      v_ch[i] <= 0;
	    final_data <= 0;
	end
	else
	begin
	    v_ch[3] <= 4'h0;
	    v_ch[2] <= v_ch[3];
	    v_ch[1] <= v_ch[2];
	    v_ch[0] <= v_ch[1];
	    
	    if (dv_enable)
	    begin
		v_ch[3] <= data_valid;
		case (data_valid)
		    4'b0001:
		      final_data <= data_cha;
		    4'b0010:	
		      final_data <= data_chb;
		    4'b0100:	
		      final_data <= data_chc;
		    4'b1000:	
		      final_data <= data_chd;
		    default:	
		      final_data <= 0;
		endcase // case(data_valid)
	    end // if (dv_enable)
	end // else: !if(reset)
    end // always @ (posedge clk or posedge reset)
endmodule