wr_clk_core.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:09:10 11/04/2005 
-- Design Name: 
-- Module Name:    wr_clk_core - structural 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity wr_clk_core is
    Port ( wr_clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           wr_clk_bufio : out  STD_LOGIC;
           wr_clk_bufr : out  STD_LOGIC;
           wr_clk_bufr_div8 : out  STD_LOGIC);
end wr_clk_core;


architecture structural of wr_clk_core is

	signal vcc: std_logic;
	signal wr_clk_bufio_i: std_logic;

begin

	vcc <= '1';
	
	wr_clk_bufio <= wr_clk_bufio_i;
	
BUFIO_inst : BUFIO
   port map (
      O => wr_clk_bufio_i,     -- Clock buffer output
      I => wr_clk      -- Clock buffer input
   );

BUFR_inst : BUFR
   generic map (
      BUFR_DIVIDE => "1",   -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" 
      SIM_DEVICE => "VIRTEX4")   -- Specify target device, "VIRTEX4" or "VIRTEX5" 
   port map (
      O => wr_clk_bufr,     -- Clock buffer output
      CE => vcc,   -- Clock enable input
      CLR => reset, -- Clock buffer reset input
      I => wr_clk_bufio_i      -- Clock buffer input
   );	

BUFR_div8_inst : BUFR
   generic map (
      BUFR_DIVIDE => "8",   -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" 
      SIM_DEVICE => "VIRTEX4")   -- Specify target device, "VIRTEX4" or "VIRTEX5" 
   port map (
      O => wr_clk_bufr_div8,     -- Clock buffer output
      CE => vcc,   -- Clock enable input
      CLR => reset, -- Clock buffer reset input
      I => wr_clk_bufio_i      -- Clock buffer input
   );


end structural;