wr_clk_core.v

来自「如何使用ISE和FPGA使用指南」· Verilog 代码 · 共 58 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:50:04 11/04/2005 
// Design Name: 
// Module Name:    wr_clk_core 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module wr_clk_core(wr_clk, reset, wr_clk_bufio, wr_clk_bufr, wr_clk_bufr_div8);
    input wr_clk;
    input reset;
    output wr_clk_bufio;
    output wr_clk_bufr;
    output wr_clk_bufr_div8;

    wire   wr_clk_bufio_i;
    
    assign wr_clk_bufio = wr_clk_bufio_i;

BUFIO BUFIO_inst (
      .O(wr_clk_bufio_i),     // Clock buffer output
      .I(wr_clk)      // Clock buffer input
   );
	
BUFR #(
      .BUFR_DIVIDE("1"), // "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" 
      .SIM_DEVICE("VIRTEX4")  // Specify target device, "VIRTEX4" or "VIRTEX5" 
   ) BUFR_inst (
      .O(wr_clk_bufr),     // Clock buffer output
      .CE(1'b1),   // Clock enable input
      .CLR(reset), // Clock buffer reset input
      .I(wr_clk_bufio_i)      // Clock buffer input
   );
	
BUFR #(
      .BUFR_DIVIDE("8"), // "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8" 
      .SIM_DEVICE("VIRTEX4")  // Specify target device, "VIRTEX4" or "VIRTEX5" 
   ) BUFR_div8_inst (
      .O(wr_clk_bufr_div8),     // Clock buffer output
      .CE(1'b1),   // Clock enable input
      .CLR(reset), // Clock buffer reset input
      .I(wr_clk_bufio_i)      // Clock buffer input
   );

endmodule