finished_v4.ucf

如何使用ISE和FPGA使用指南

#######################################################################
#
#		Step 1
#	Global Timing Constraints
#
#######################################################################

#NET "rd_clk" TNM_NET = "rd_clk";
#TIMESPEC "TS_rd_clk" = PERIOD "rd_clk" 3 ns HIGH 50 %;
#OFFSET = OUT 2.5 ns AFTER "rd_clk"  ;
#NET "wr_clk_chd" TNM_NET = "wr_clk_chd";
#TIMESPEC "TS_wr_clk_chd" = PERIOD "wr_clk_chd" 6 ns HIGH 50 %;
#OFFSET = IN 4 ns BEFORE "wr_clk_chd"  ;
#OFFSET = IN 4 ns BEFORE "wr_clk_chc"  ;
#OFFSET = IN 4 ns BEFORE "wr_clk_chb"  ;
#OFFSET = IN 4 ns BEFORE "wr_clk_cha"  ;
#NET "wr_clk_chc" TNM_NET = "wr_clk_chc";
#TIMESPEC "TS_wr_clk_chc" = PERIOD "wr_clk_chc" 6 ns HIGH 50 %;
#NET "wr_clk_chb" TNM_NET = "wr_clk_chb";
#TIMESPEC "TS_wr_clk_chb" = PERIOD "wr_clk_chb" 6 ns HIGH 50 %;
#NET "wr_clk_cha" TNM_NET = "wr_clk_cha";
#TIMESPEC "TS_wr_clk_cha" = PERIOD "wr_clk_cha" 6 ns HIGH 50 %;

#######################################################################
#
#		Pin Assignments
#
#######################################################################

#NET "data_cha" LOC = "K1" ;
#NET "data_chb" LOC = "F3" ;
#NET "data_chc" LOC = "K20" ;
#NET "data_chd" LOC = "F18" ;
#NET "reset" LOC = "N18" ;
#NET "final_data<0>" LOC = "A7" ;
#NET "final_data<1>" LOC = "A14" ;
#NET "final_data<2>" LOC = "B14" ;
#NET "final_data<3>" LOC = "B8" ;
#NET "final_data<4>" LOC = "A8" ;
#NET "final_data<5>" LOC = "A13" ;
#NET "final_data<6>" LOC = "B13" ;
#NET "final_data<7>" LOC = "C10" ;
#NET "wr_clk_chd" LOC = "B19" ;
#NET "wr_clk_chc" LOC = "K18" ;
#NET "wr_clk_chb" LOC = "B2" ;
#NET "wr_clk_cha" LOC = "M4" ;
#NET "valid_ch<3>" LOC = "B9" ;
#NET "valid_ch<2>" LOC = "C11" ;
#NET "valid_ch<1>" LOC = "B11" ;
#NET "valid_ch<0>" LOC = "B10" ;
#NET "reset" LOC = "N18" ;
#NET "mac_dv<3>" LOC = "B15" ;
#NET "mac_dv<2>" LOC = "K19" ;
#NET "mac_dv<1>" LOC = "M18" ;
#NET "mac_dv<0>" LOC = "L5" ;
#NET "mac_chd<20>" LOC = "A15" ;
#NET "mac_chd<19>" LOC = "A16" ;
#NET "mac_chd<18>" LOC = "B16" ;
#NET "mac_chd<17>" LOC = "C15" ;
#NET "mac_chd<16>" LOC = "C16" ;
#NET "mac_chd<15>" LOC = "B17" ;
#NET "mac_chd<14>" LOC = "C17" ;
#NET "mac_chd<13>" LOC = "D16" ;
#NET "mac_chd<12>" LOC = "E16" ;
#NET "mac_chd<11>" LOC = "A18" ;
#NET "mac_chd<10>" LOC = "B18" ;
#NET "mac_chd<9>" LOC = "D17" ;
#NET "mac_chd<8>" LOC = "D18" ;
#NET "mac_chd<7>" LOC = "C20" ;
#NET "mac_chd<6>" LOC = "C18" ;
#NET "mac_chd<5>" LOC = "C19" ;
#NET "mac_chd<4>" LOC = "F16" ;
#NET "mac_chd<3>" LOC = "F17" ;
#NET "mac_chd<2>" LOC = "D19" ;
#NET "mac_chd<1>" LOC = "E19" ;
#NET "mac_chd<0>" LOC = "G16" ;
#NET "mac_chc<20>" LOC = "G17" ;
#NET "mac_chc<19>" LOC = "E20" ;
#NET "mac_chc<18>" LOC = "F20" ;
#NET "mac_chc<17>" LOC = "H16" ;
#NET "mac_chc<16>" LOC = "H17" ;
#NET "mac_chc<15>" LOC = "F19" ;
#NET "mac_chc<14>" LOC = "G19" ;
#NET "mac_chc<13>" LOC = "J17" ;
#NET "mac_chc<12>" LOC = "J18" ;
#NET "mac_chc<11>" LOC = "H20" ;
#NET "mac_chc<10>" LOC = "G20" ;
#NET "mac_chc<9>" LOC = "J15" ;
#NET "mac_chc<8>" LOC = "J16" ;
#NET "mac_chc<7>" LOC = "H18" ;
#NET "mac_chc<6>" LOC = "H19" ;
#NET "mac_chc<5>" LOC = "K16" ;
#NET "mac_chc<4>" LOC = "K17" ;
#NET "mac_chc<3>" LOC = "M20" ;
#NET "mac_chc<2>" LOC = "L20" ;
#NET "mac_chc<1>" LOC = "M15" ;
#NET "mac_chc<0>" LOC = "M16" ;
#NET "mac_chb<20>" LOC = "B6" ;
#NET "mac_chb<19>" LOC = "A6" ;
#NET "mac_chb<18>" LOC = "A5" ;
#NET "mac_chb<17>" LOC = "B5" ;
#NET "mac_chb<16>" LOC = "C6" ;
#NET "mac_chb<15>" LOC = "C5" ;
#NET "mac_chb<14>" LOC = "B4" ;
#NET "mac_chb<13>" LOC = "C4" ;
#NET "mac_chb<12>" LOC = "D5" ;
#NET "mac_chb<11>" LOC = "E5" ;
#NET "mac_chb<10>" LOC = "A3" ;
#NET "mac_chb<9>" LOC = "B3" ;
#NET "mac_chb<8>" LOC = "D4" ;
#NET "mac_chb<7>" LOC = "D3" ;
#NET "mac_chb<6>" LOC = "C3" ;
#NET "mac_chb<5>" LOC = "C2" ;
#NET "mac_chb<4>" LOC = "F5" ;
#NET "mac_chb<3>" LOC = "F4" ;
#NET "mac_chb<2>" LOC = "D2" ;
#NET "mac_chb<1>" LOC = "E2" ;
#NET "mac_chb<0>" LOC = "G5" ;
#NET "mac_cha<20>" LOC = "G4" ;
#NET "mac_cha<19>" LOC = "E1" ;
#NET "mac_cha<18>" LOC = "F1" ;
#NET "mac_cha<17>" LOC = "H5" ;
#NET "mac_cha<16>" LOC = "H4" ;
#NET "mac_cha<15>" LOC = "F2" ;
#NET "mac_cha<14>" LOC = "G2" ;
#NET "mac_cha<13>" LOC = "J4" ;
#NET "mac_cha<12>" LOC = "J3" ;
#NET "mac_cha<11>" LOC = "H1" ;
#NET "mac_cha<10>" LOC = "G1" ;
#NET "mac_cha<9>" LOC = "J6" ;
#NET "mac_cha<8>" LOC = "J5" ;
#NET "mac_cha<7>" LOC = "H3" ;
#NET "mac_cha<6>" LOC = "H2" ;
#NET "mac_cha<5>" LOC = "K5" ;
#NET "mac_cha<4>" LOC = "K4" ;
#NET "mac_cha<3>" LOC = "K3" ;
#NET "mac_cha<2>" LOC = "K2" ;
#NET "mac_cha<1>" LOC = "M3" ;
#NET "mac_cha<0>" LOC = "M1" ;

########################################################################
#
# 		Step 2 
# Specify multi-cycle paths from the blockrams to ffs
#
########################################################################

#TIMESPEC "ts_blockrams2ffs" = FROM "RAMS" TO "FFS" "TS_rd_clk" * 3;

########################################################################
#
# 		Step 3 
# The outputs are active for 8 rd_clk cycles.  The valid signals
# are active for 4 clock cycles.  Allow two internal clock cycles to 
# propagate these values off chip (multi-cycle path).
#
# NOTE...To constraint these paths we just added pads to the group.  No
# new constraints were needed since the offset out already exists.
#
########################################################################

INST "final_data*.PAD" TNM = "tgrp_output_data";
INST "mac_ch?*.PAD" TNM = "tgrp_output_data";
INST "valid_ch*.PAD" TNM = "tgrp_output_data";
#INST "mac_dv*.PAD" TNM = "tgrp_output_data_data";
#TIMEGRP "tgrp_output_data_data" OFFSET = OUT 6 ns AFTER "rd_clk";


########################################################################
#
# 		Step 4 
# Specify multi-cycle paths for the clock enable signals waiting_cntr_en
# to next_ch_en.
#
########################################################################

#NET "data_control_inst/waiting_cntr_en" TNM_NET = "tgrp_waiting_cntr_en";
#NET "data_control_inst/next_ch_en" TNM_NET = "tgrp_next_ch_en";
#TIMESPEC "ts_waiting_cntr_en_grp2next_ch_en_grp" = FROM "tgrp_waiting_cntr_en" TO "tgrp_next_ch_en" "TS_rd_clk" * 5;

########################################################################
#
# 		Step 5 
# Specify multi-cycle paths for all ffs driven by dv_enable signal
# 
########################################################################

NET "data_control_inst/dv_enable" TNM_NET = "tgrp_dv_enable";
TIMESPEC "ts_dv_enable2dv_enable" = FROM "tgrp_dv_enable" TO "tgrp_dv_enable" "TS_rd_clk" * 8;