finished_s3.ucf

如何使用ISE和FPGA使用指南

########################################################################
#
#		Step 1
#	Global Timing Constraints
#
########################################################################

#NET "rd_clk" TNM_NET = "rd_clk";
#TIMESPEC "TS_rd_clk" = PERIOD "rd_clk" 8.75 ns HIGH 50 %;
#OFFSET = OUT 5 ns AFTER "rd_clk"  ;
#NET "wr_clk_cha" TNM_NET = "wr_clk_cha";
#TIMESPEC "TS_wr_clk_cha" = PERIOD "wr_clk_cha" 15 ns HIGH 50 %;
#NET "wr_clk_chb" TNM_NET = "wr_clk_chb";
#TIMESPEC "TS_wr_clk_chb" = PERIOD "wr_clk_chb" 15 ns HIGH 50 %;
#NET "wr_clk_chc" TNM_NET = "wr_clk_chc";
#TIMESPEC "TS_wr_clk_chc" = PERIOD "wr_clk_chc" 15 ns HIGH 50 %;
#NET "wr_clk_chd" TNM_NET = "wr_clk_chd";
#TIMESPEC "TS_wr_clk_chd" = PERIOD "wr_clk_chd" 15 ns HIGH 50 %;
#OFFSET = IN 7.5 ns BEFORE "wr_clk_chd"  ;
#OFFSET = IN 7.5 ns BEFORE "wr_clk_chc"  ;
#OFFSET = IN 7.5 ns BEFORE "wr_clk_chb"  ;
#OFFSET = IN 7.5 ns BEFORE "wr_clk_cha"  ;

#########################################################################
#
#		Pin Assignments
#
#########################################################################

#NET "data_cha" LOC = "m3";
#NET "data_chb" LOC = "j16";
#NET "data_chc" LOC = "p15";
#NET "data_chd" LOC = "j1";
#NET "final_data[0]" LOC = "b11";
#NET "final_data[1]" LOC = "a10";
#NET "final_data[2]" LOC = "a7";
#NET "final_data[3]" LOC = "a9";
#NET "final_data[4]" LOC = "c8";
#NET "final_data[5]" LOC = "j4";
#NET "final_data[6]" LOC = "b10";
#NET "final_data[7]" LOC = "d8";
#NET "mac_cha[0]" LOC = "p1";
#NET "mac_cha[10]" LOC = "e10";
#NET "mac_cha[11]" LOC = "c5";
#NET "mac_cha[12]" LOC = "b5";
#NET "mac_cha[13]" LOC = "c10";
#NET "mac_cha[14]" LOC = "c7";
#NET "mac_cha[15]" LOC = "e7";
#NET "mac_cha[16]" LOC = "b6";
#NET "mac_cha[17]" LOC = "a5";
#NET "mac_cha[18]" LOC = "e6";
#NET "mac_cha[19]" LOC = "d6";
#NET "mac_cha[1]" LOC = "f2";
#NET "mac_cha[20]" LOC = "d7";
#NET "mac_cha[2]" LOC = "f3";
#NET "mac_cha[3]" LOC = "g2";
#NET "mac_cha[4]" LOC = "h3";
#NET "mac_cha[5]" LOC = "f5";
#NET "mac_cha[6]" LOC = "d10";
#NET "mac_cha[7]" LOC = "b7";
#NET "mac_cha[8]" LOC = "d5";
#NET "mac_cha[9]" LOC = "c6";
#NET "mac_chb[0]" LOC = "p2";
#NET "mac_chb[10]" LOC = "a12";
#NET "mac_chb[11]" LOC = "d16";
#NET "mac_chb[12]" LOC = "g13";
#NET "mac_chb[13]" LOC = "e13";
#NET "mac_chb[14]" LOC = "f14";
#NET "mac_chb[15]" LOC = "f15";
#NET "mac_chb[16]" LOC = "e14";
#NET "mac_chb[17]" LOC = "f13";
#NET "mac_chb[18]" LOC = "e15";
#NET "mac_chb[19]" LOC = "f12";
#NET "mac_chb[1]" LOC = "h14";
#NET "mac_chb[20]" LOC = "e16";
#NET "mac_chb[2]" LOC = "h15";
#NET "mac_chb[3]" LOC = "h13";
#NET "mac_chb[4]" LOC = "h16";
#NET "mac_chb[5]" LOC = "g15";
#NET "mac_chb[6]" LOC = "g14";
#NET "mac_chb[7]" LOC = "b12";
#NET "mac_chb[8]" LOC = "g16";
#NET "mac_chb[9]" LOC = "g12";
#NET "mac_chc[0]" LOC = "n3";
#NET "mac_chc[10]" LOC = "t10";
#NET "mac_chc[11]" LOC = "t12";
#NET "mac_chc[12]" LOC = "m11";
#NET "mac_chc[13]" LOC = "p8";
#NET "mac_chc[14]" LOC = "p9";
#NET "mac_chc[15]" LOC = "t9";
#NET "mac_chc[16]" LOC = "p11";
#NET "mac_chc[17]" LOC = "r10";
#NET "mac_chc[18]" LOC = "r11";
#NET "mac_chc[19]" LOC = "p10";
#NET "mac_chc[1]" LOC = "m10";
#NET "mac_chc[20]" LOC = "n9";
#NET "mac_chc[2]" LOC = "p12";
#NET "mac_chc[3]" LOC = "r12";
#NET "mac_chc[4]" LOC = "n12";
#NET "mac_chc[5]" LOC = "t14";
#NET "mac_chc[6]" LOC = "t8";
#NET "mac_chc[7]" LOC = "n11";
#NET "mac_chc[8]" LOC = "n10";
#NET "mac_chc[9]" LOC = "r9";
#NET "mac_chd[0]" LOC = "n2";
#NET "mac_chd[10]" LOC = "g3";
#NET "mac_chd[11]" LOC = "g5";
#NET "mac_chd[12]" LOC = "e2";
#NET "mac_chd[13]" LOC = "g4";
#NET "mac_chd[14]" LOC = "d3";
#NET "mac_chd[15]" LOC = "e3";
#NET "mac_chd[16]" LOC = "d2";
#NET "mac_chd[17]" LOC = "c3";
#NET "mac_chd[18]" LOC = "f4";
#NET "mac_chd[19]" LOC = "d1";
#NET "mac_chd[1]" LOC = "k2";
#NET "mac_chd[20]" LOC = "e4";
#NET "mac_chd[2]" LOC = "k3";
#NET "mac_chd[3]" LOC = "k4";
#NET "mac_chd[4]" LOC = "k1";
#NET "mac_chd[5]" LOC = "k5";
#NET "mac_chd[6]" LOC = "e1";
#NET "mac_chd[7]" LOC = "h4";
#NET "mac_chd[8]" LOC = "j2";
#NET "mac_chd[9]" LOC = "h1";
#NET "mac_dv[0]" LOC = "g1";
#NET "mac_dv[1]" LOC = "t13";
#NET "mac_dv[2]" LOC = "j13";
#NET "mac_dv[3]" LOC = "l3";
#NET "rd_clk" LOC = "n8";
#NET "reset" LOC = "r1";
#NET "valid_ch[0]" LOC = "r6";
#NET "valid_ch[1]" LOC = "j3";
#NET "valid_ch[2]" LOC = "c11";
#NET "valid_ch[3]" LOC = "e11";
#NET "wr_clk_cha" LOC = "d9";
#NET "wr_clk_chb" LOC = "c9";
#NET "wr_clk_chc" LOC = "a8";
#NET "wr_clk_chd" LOC = "b8";

########################################################################
# 
#		Step 2
# Multi-cycle paths from the blockrams to ffs
#
########################################################################

#TIMESPEC "TS_blockrams2ffs" = FROM "RAMS" TO "FFS" "TS_rd_clk" * 3;

########################################################################
# 
#		Step 3
# The outputs are active for 8 rd_clk cycles.  The valid signals
# are active for 4 clock cycles.  Allow two internal clock cycles to 
# propagate these values off chip (multi-cycle path).
# You put the valid_ch* outputs into a group using the Constraints
# Editor.  These constraints add more outputs into the same group.
#
########################################################################

INST "final_data*.PAD" TNM = "tgrp_output_data";
INST "mac_ch?*.PAD" TNM = "tgrp_output_data";
#INST "mac_dv*.PAD" TNM = "tgrp_output_data";
INST "valid_ch*.PAD" TNM = "tgrp_output_data";
#TIMEGRP "tgrp_output_data" OFFSET = OUT 10 ns AFTER "rd_clk";

########################################################################
#
#		Step 4
# Multi-cycle paths for the clock enable signals waiting_cntr_en
# to next_ch_en. This constraint adds more flip-flops to the tgrp_waiting_cntr_en
# group.
#
########################################################################

NET "data_control_inst/data_control_fsm_inst/waiting_cntr_en_3" TNM_NET = "tgrp_waiting_cntr_en";
#NET "data_control_inst/waiting_cntr_en" TNM_NET = "tgrp_waiting_cntr_en";
#NET "data_control_inst/next_ch_en" TNM_NET = "tgrp_next_ch_en";
#TIMESPEC "TS_waiting_cntr_en_grp2next_ch_en_grp" = FROM "tgrp_waiting_cntr_en" TO "tgrp_next_ch_en" "TS_rd_clk" * 5;

########################################################################
#
#		Step 5
# Multi-cycle paths for all ffs driven by dv_enable signal 
#
########################################################################

NET "data_control_inst/dv_enable" TNM_NET = "tgrp_dv_enable";
NET "data_control_inst/mac_inst/mac_cha_inst/dv_enable??" TNM_NET = "tgrp_dv_enable";
TIMESPEC "TS_dv_enable2dv_enable" = FROM "tgrp_dv_enable" TO "tgrp_dv_enable" "TS_rd_clk" * 8;