📄 dds.fit.rpt
字号:
; 11 ; 4 ;
; 12 ; 0 ;
; 13 ; 1 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 1 ;
; 17 ; 1 ;
+---------------------------------------------+------------------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+----------------------------+
; Advanced Data - General ;
+--------------------+-------+
; Name ; Value ;
+--------------------+-------+
; Status Code ; 0 ;
; Desired User Slack ; 0 ;
; Fit Attempts ; 1 ;
+--------------------+-------+
+-----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation ;
+--------------------------------------------------------------------------------+--------------+
; Name ; Value ;
+--------------------------------------------------------------------------------+--------------+
; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 31 ;
; Mid Slack - Fit Attempt 1 ; -19397 ;
; Internal Atom Count - Fit Attempt 1 ; 161 ;
; LE/ALM Count - Fit Attempt 1 ; 161 ;
; LAB Count - Fit Attempt 1 ; 19 ;
; Outputs per Lab - Fit Attempt 1 ; 4.895 ;
; Inputs per LAB - Fit Attempt 1 ; 7.947 ;
; Global Inputs per LAB - Fit Attempt 1 ; 0.632 ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1 ; 0:19 ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1 ; 0:15;1:4 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:14;1:5 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1 ; 0:14;1:5 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1 ; 0:14;1:5 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1 ; 0:14;1:5 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1 ; 0:18;1:1 ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1 ; 0:19 ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1 ; 0:15;1:4 ;
; LAB Constraint 'global control signals' - Fit Attempt 1 ; 0:8;1:10;2:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:8;1:9;2:2 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1 ; 0:19 ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1 ; 0:8;1:11 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1 ; 0:17;1:2 ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1 ; 0:1;1:18 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:17;1:2 ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:19 ;
; LEs in Chains - Fit Attempt 1 ; 50 ;
; LEs in Long Chains - Fit Attempt 1 ; 16 ;
; LABs with Chains - Fit Attempt 1 ; 6 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
+--------------------------------------------------------------------------------+--------------+
+----------------------------------------------+
; Advanced Data - Placement ;
+-------------------------------------+--------+
; Name ; Value ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
; Early Wire Use - Fit Attempt 1 ; 8 ;
; Early Slack - Fit Attempt 1 ; -22303 ;
; Auto Fit Point 3 - Fit Attempt 1 ; ff ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 16 ;
; Mid Slack - Fit Attempt 1 ; -20446 ;
; Late Wire Use - Fit Attempt 1 ; 18 ;
; Late Slack - Fit Attempt 1 ; -20446 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.032 ;
+-------------------------------------+--------+
+----------------------------------------------+
; Advanced Data - Routing ;
+-------------------------------------+--------+
; Name ; Value ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1 ; -18035 ;
; Early Wire Use - Fit Attempt 1 ; 15 ;
; Peak Regional Wire - Fit Attempt 1 ; 14 ;
; Mid Slack - Fit Attempt 1 ; -20577 ;
; Late Slack - Fit Attempt 1 ; -20577 ;
; Late Wire Use - Fit Attempt 1 ; 18 ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.187 ;
+-------------------------------------+--------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Mon Feb 16 16:36:13 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dds -c dds
Info: Selected device EPM240T100C5 for design "dds"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal "cp_65k" to use Global clock
Info: Destination "cp_65k" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "cp_1k" to use Global clock
Info: Destination "cp_1k" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 11.530 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y3; Fanout = 38; REG Node = 'dds_add[12]'
Info: 2: + IC(2.219 ns) + CELL(0.200 ns) = 2.419 ns; Loc. = LAB_X7_Y3; Fanout = 1; COMB Node = 'Mux33~351'
Info: 3: + IC(2.039 ns) + CELL(0.200 ns) = 4.658 ns; Loc. = LAB_X5_Y3; Fanout = 1; COMB Node = 'Mux33~352'
Info: 4: + IC(1.069 ns) + CELL(0.511 ns) = 6.238 ns; Loc. = LAB_X6_Y3; Fanout = 1; COMB Node = 'Mux33~354'
Info: 5: + IC(0.440 ns) + CELL(0.740 ns) = 7.418 ns; Loc. = LAB_X6_Y3; Fanout = 1; COMB Node = 'data~466'
Info: 6: + IC(1.790 ns) + CELL(2.322 ns) = 11.530 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'data[0]'
Info: Total cell delay = 3.973 ns ( 34.46 % )
Info: Total interconnect delay = 7.557 ns ( 65.54 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 13% of the available device resources. Peak interconnect usage is 13%
Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin cs has GND driving its datain port
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
Info: Allocated 157 megabytes of memory during processing
Info: Processing ended: Mon Feb 16 16:36:17 2009
Info: Elapsed time: 00:00:04
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/CPLD/例程/实际例程/9正弦波发生电路/dds.fit.smsg.
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