cs8900_enet_if_driver.h

sharp的arm920t 7A400的评估板附带光盘Sharp KEVLH7A400 v0.3b Welcome to the SHARP KEV7A400 Evaluation board

/**********************************************************************
 *  $Workfile:   CS8900_enet_if_driver.h  $
 *  $Revision:   1.1  $
 *  $Author:   MaysR  $
 *  $Date:   Aug 29 2002 08:57:54  $
 *
 *  Project: 
 *
 *  Description:  
 *
 *	References:
 *
 *	Revision History:
 *	$Log:   //smaicnt2/pvcs/VM/CHIPS/archives/LH7A400/Ethernet/Drivers/CS8900_enet_if_driver.h-arc  $
 * 
 *    Rev 1.1   Aug 29 2002 08:57:54   MaysR
 * Corrected parameter types for set IRQ and set DMA functions.
 * 
 *    Rev 1.0   Aug 27 2002 11:41:04   MaysR
 * Initial revision.
 * 
 * 
 *	COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *		CAMAS, WA
 *
 *********************************************************************/

#ifndef CS8900_ENET_IF_DRIVER_H
#define CS8900_ENET_IF_DRIVER_H

#include "SMA_Types.h"

/**********************************************************************
 * PacketPage register layout
 *********************************************************************/
// The following structures are not too useful for an IO mapped
// architecture, but they can be used to determine offsets in the
// PacketPage atructures to registers and data.

// CS8900A bus interface control registers
// Address range 0x0000 - 0x00FE
typedef struct
{
   UNS_16        chip_id_h;       // Chip ID register high
   UNS_16        chip_id_l;       // Chip ID register low
   UNS_16        reserved_1 [14];
   UNS_16        io_base_addr;    // IO base address
   UNS_16        int_num;         // Interrupt number
   UNS_16        dma_channel;     // DMA channel
   UNS_16        dma_sof;         // DMA start of frame
   UNS_16        dma_frame_cnt;   // DMA frame count
   UNS_16        dma_byte_cnt;    // DMA byte count
   UNS_16        mem_base_h;      // Memory base address high
   UNS_16        mem_base_l;      // Memory base address low
   UNS_16        boot_pr_addr_h;  // Boot PROM base address high
   UNS_16        boot_pr_addr_l;  // Boot PROM base address low
   UNS_16        boot_pr_mask_h;  // Bot PROM address mask high
   UNS_16        boot_pr_mask_l;  // Bot PROM address mask low
   UNS_16        reserved_2 [4];
   UNS_16        eeprom_cmd;      // EEPROM command
   UNS_16        eeprom_data;     // EEPROM data
   UNS_16        reserved_3 [6];
   UNS_16        rxfr_byte_cnt;   // RX frame byte count
   UNS_16        reserved_4 [87];
} enet_8900bus_t;

// CS8900A status and control registers
// Address range 0x0100 - 0x0142
typedef struct
{
   UNS_16        reserved_1;
   UNS_16        reg3_rxcfg;      // Register 3 - RXCFG
   UNS_16        reg5_rxctl;      // Register 5 - RXCTL
   UNS_16        reg7_txcfg;      // Register 7 - TXCFG
   UNS_16        reg9_txcmd;      // Register 9 - TXCMD (status)
   UNS_16        regb_bufcfg;     // Register B - BufCFG
   UNS_16        reserved_2 [3];
   UNS_16        reg13_linectl;   // Register 13 - LineCTL
   UNS_16        reg15_selfctl;   // Register 15 - SelfCTL
   UNS_16        reg17_busctl;    // Register 17 - BusCTL
   UNS_16        reg19_testctl;   // Register 19 - TestCTL
   UNS_16        reserved_3 [3];
   UNS_16        reg0_isq;        // Register 0 - Interrupt status Queue
   UNS_16        reserved_4;
   UNS_16        reg4_rxevent;    // Register 4 - RxEvent
   UNS_16        reserved_5;
   UNS_16        reg8_txevent;    // Register 8 - TxEvent
   UNS_16        reserved_6;
   UNS_16        regc_bufevent;   // Register C - BufEvent
   UNS_16        reserved_7;
   UNS_16        reg10_rxmiss;    // Register 10 - RX miss counter
   UNS_16        reg12_txcol;     // Register 12 - TX collision clear
   UNS_16        reg14_linest;    // Register 14 - Line status
   UNS_16        reg16_selfst;    // Register 16 - Self status
   UNS_16        reg18_busst;     // Register 18 - Bus status
   UNS_16        reserved_8;
   UNS_16        reg1c_tdr;       // Register 1C - TDR counter
   UNS_16        reserved_9 [3];
} enet_8900stco_t;

// CS8900A transmit initiate registers
// Address range 0x0144 - 0x014E
typedef struct
{
   UNS_16        txcmd;           // Transmit command
   UNS_16        txlen;           // Transmit length
   UNS_16        reserved_1 [4];
} enet_8900tran_t;

// CS8900A address filter registers
// Address range 0x0150 - 0x015E
typedef struct
{
   UNS_8         hash_filter [8]; // Logical address filter
   UNS_8         enet_address [6];// Ethernet IEEE address
   UNS_8         reserved_1 [674];
} enet_8900filter_t;

// CS8900A Frame location(s)
// Address range 0x0400 - 0x0A00
typedef struct
{
   UNS_16        rx_status;       // Receive status
   UNS_16        rxlen;           // Receive length
   UNS_16        rxfr_loc [0xA00 - 0x404];
                                  // Receive frame location
   UNS_16        txfr_loc;        // Transmit frame location
} enet_8900frame_t;

// List of read ports
typedef enum 
{
    rxd0, 
    rxd1, 
    unused_r1, 
    unused_r2, 
    isq, 
    ppptr, 
    pd0, 
    pd1
} rx_port_t;

// List of write ports - ppptr, pd0, and pd1 are shared with read enums
typedef enum 
{
    txd0, 
    txd1, 
    txcmd, 
    txlen, 
    unused_t1
} tx_port_t;

// CS8900 PacketPage structure
typedef struct
{
   enet_8900bus_t     bus_regs;
   enet_8900stco_t    stco_regs;
   enet_8900tran_t    tx_regs;
   enet_8900filter_t  filter_regs;
   enet_8900frame_t   frame_regs;
} enet_pp_t;

/**********************************************************************
 * Register attributes and layout - bus interface registers
 *********************************************************************/
 
// Interrupt values - int_num register
typedef enum 
{
    INTR0 = 0x0, 
    INTR1 = 0x1, 
    INTR2 = 0x2, 
    INTR3 = 0x3,
    INTR_NONE = 0x4
} enet_int_t;

// DMA values - dma_channel register
typedef enum 
{
    DMA0 = 0x0, 
    DMA1 = 0x1, 
    DMA2 = 0x2,
    DMA_NONE = 0x3
} enet_dma_t;

extern enet_pp_t *enet_pp_data;

/**********************************************************************
 * Register identification
 *********************************************************************/

/* Register 0 - Interrupt status queue bits - this mask is also shared
 * with all the individual status and control registers and the 
 * Interrupt status queue port register - the value obtained with this 
 * mask is used to identify the source of an interrupt and where the 
 * data for the interrupt resides
*/ 
#define REGNUM_MASK       0x003F    // Interrupt # mask (reg number)

/* Register identification list - obtained from the interrupt status 
 * queue or an individual register and the REGNUM_MASK mask value. In 
 * general, status registers are Read-Only (RO), while control and 
 * configuration registers are Read-Write (RW). When an interrupt 
 * occurs, the lower 6 bits of the interrupt status queue (masked with 
 * REGNUM_MASK) will designate which register contains the information 
 * for the present interrupt.
*/
#define RRXCFG            0x0003    // Receiver config register     (RW)
#define RRXEVENT          0x0004    // Receiver event status reg    (RO)
#define RRXCTL            0x0005    // Receiver control register    (RW)
#define RTXCFG            0x0007    // Transmitter config reg       (RW)
#define RTXEVENT          0x0008    // Transmitter event status reg (RO)
#define RTXCMD            0x0009    // Transmit command status reg  (RO)
#define RBUFCFG           0x000B    // Buffer configuration reg     (RW)
#define RBUFEVENT         0x000C    // Buffer event status register (RO)
#define RRXMISS           0x0010    // RX missed frame status reg   (RO)
#define TXCMD             0x0011    // TX command reg               (WO)
#define RTXCOL            0x0012    // TX collision count reg       (RO)
#define RLINECTL          0x0013    // Line control register        (RW)
#define RLINEST           0x0014    // Line status register         (RO)
#define RSELFCTL          0x0015    // Self control register        (RW)
#define RSELFST           0x0016    // Self status register         (RO)
#define RBUSCTL           0x0017    // Bus control register         (RW)
#define RBUSST            0x0018    // Bus status register          (RO)
#define RTESTCTL          0x0019    // Test control register        (RW)
#define RAUIRELF          0x001C    // AUI TDR register             (RO)

/**********************************************************************
 * Register attributes and layout - Control registers
 *********************************************************************/

// Register 3 - Receiver configuration bits
#define SKIP_1         0x0040 // Delete last received frame
#define STREAME        0x0080 // Auto transfer frames via DMA
#define RXOKIE         0x0100 // Intr when good RX frame received
#define RXDMA_ONLY     0x0200 // Use DMA only for RX frames
#define AUTORX_DMAE    0x0400 // Auto-switch to DMA for receive
#define BUFFERCRC      0x0800 // Include CRC in RX buffer
#define CRCERRORIE     0x1000 // Interrupt on RX frame CRC error
#define RUNTIE         0x2000 // Interrupt on short RX frame
#define EXTADATAIE     0x4000 // Interrupt on long RX frame

// Register 5 - Receiver control bits
#define IAHASHA        0x0040 // Accept frames that pass hash filter
#define PROMISUCOUSA   0x0080 // Accept all incoming frames
#define RXOKA          0x0100 // Accept valid RX frames
#define MULTICASTA     0x0200 // Accept multicast frames that pass hash
#define INDIVIDUALA    0x0400 // Accept frames that pass individual addr
#define BROADCASTA     0x0800 // Accept broadcase frames
#define CRCERRORA      0x1000 // Accept frames with a bad CRC
#define RUNTA          0x2000 // Accept short frames
#define EXTADATAA      0x4000 // Accept long frames

// Register 7 - Transmitter configuration bits
#define LOSSOFCRIE     0x0040 // Interrupt on loss of carrier (on TX)
#define SQERRORIE      0x0080 // Interrupt on SQE error
#define TXOKIE         0x0100 // Interrupt on good TX frame completion
#define OUTOFWINDOWIE  0x0200 // Interrupt on late collision
#define JABBERIE       0x0400 // Interrupt on long transmission (time)
#define ANYCOLLIE      0x0800 // Interrupt on any collision (on TX)
#define COLL16IE       0x8000 // Interrupt on 16th collision (on TX)

// Register B - Buffer configuration bits
#define SWINT_X        0x0040 // Generate an interrupt (software)
#define RXDMAIE        0x0080 // Interrupt on RX frame DMA complete
#define RDY4TXIE       0x0100 // Interrupt when ready for next TX frame
#define TXUNDERRUNIE   0x0200 // Interrupt TX frame underrun error
#define RXMISSIE       0x0400 // Interrupt on missed RX frame