lh7a400_ssp_driver.h

sharp的arm920t 7A400的评估板附带光盘Sharp KEVLH7A400 v0.3b Welcome to the SHARP KEV7A400 Evaluation board

/**********************************************************************
 *	$Workfile:   lh7a400_ssp_driver.h  $
 *	$Revision:   1.3  $
 *	$Author:   KovitzP  $
 *	$Date:   Nov 20 2001 18:37:54  $
 *
 *	Project: LH79520 and eval board test
 *
 *	Description:
 *     This file contains driver support for the Synchronous
 *     Serial Port (SSP) on the LH79520. Functions are described below
 *	References:
 *		(1) ARM PrimeCell Synchronous Serial Port (PL020)
 *		Technical Reference Manual, ARM DDI 0141C.
 *    (2) Sharp/Parthus Internal document Alpheus2 Specification v0.71
 *
 *	Revision History:
 *	$Log:   P:/PVCS6_6/archives/LH7A400 (Aruba)/SSP/lh7a400_ssp_driver.h-arc  $
 * 
 *    Rev 1.3   Nov 20 2001 18:37:54   KovitzP
 * removed commented out and unimplemented function headers
 * 
 *    Rev 1.2   Nov 19 2001 10:25:24   KovitzP
 * Corrected bugs in interrupt enable/disable functions. Removed
 * some dead code for installing interrupt handlers.
 * 
 *    Rev 1.1   Nov 14 2001 09:01:46   KovitzP
 * Modified include hierarchy
 * 
 *    Rev 1.0   Nov 12 2001 13:32:10   KovitzP
 * Initial revision.
 * 
 * 
 *	COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *		CAMAS, WA
 *********************************************************************/
#ifndef LH7A400_SSP_DRIVER_H
#define LH7A400_SSP_DRIVER_H
#include "LH7A400_map.h"
/* define clock divider and prescaler maxima and minima */
#define SSP_PRESCALE_MAX 254
#define SSP_PRESCALE_MIN 2
#define SSP_DIVIDER_MAX 256
#define MAX_SSP_FREQ (sspclk / SSP_PRESCALE_MIN)

/* 
initialization functions 
*/
void ssp_init_spi_mode(void);
void ssp_init_uwire_mode(void);
void ssp_init_ti_mode(void);
void ssp_disable(void);
void ssp_enable(void);

/* control functions */
INT_32 ssp_set_bits_per_word(INT_32 nbits); /* returns previous value */
INT_32 ssp_get_bits_per_word(void);
void ssp_loopback_on(void);
void ssp_loopback_off(void);

/* 
clock output speed. 
*/
INT_32 ssp_set_speed(INT_32 requested_bits_per_second);
INT_32 ssp_get_speed(void);

/* 
SPI-specific control functions 
(see ARM prime cell pl020 TRM,
reference ARM DDI 0141C,
figures 2-6 and 2-7)
*/
void ssp_spi_set_spo(void);
void ssp_spi_clr_spo(void);
void ssp_spi_set_sph(void);
void ssp_spi_clr_sph(void);

/*
Interrupt control
*/
void ssp_int_enable_receive_overflow(void);
void ssp_int_disable_receive_overflow(void);
void ssp_int_enable_receive(void);
void ssp_int_disable_receive(void);
void ssp_int_enable_transmit(void);
void ssp_int_disable_transmit(void);
void ssp_int_enable_transmit_idle(void);
void ssp_int_disable_transmit_idle(void);
void ssp_int_disable_all(void);

/*
FIFO control
*/
void ssp_disable_fifos(void);
void ssp_enable_fifos(void);
void ssp_flush_fifos(void);

/* transmit data */
void ssp_transmit(UNS_16 data);
void ssp_transmit_block(UNS_16 *data, INT_32 wordcount);

/* receive data */
UNS_16 ssp_receive(void);
INT_32 ssp_receive_block(UNS_16 *data, INT_32 wordcount);

/* transceive data */
UNS_16 ssp_transceive(UNS_16 data);
void ssp_transceive_block(UNS_16 *data_in, 
						  UNS_16 *data_out, 
			              INT_32 wordcount);

/* status */
INT_32 ssp_fifos_enabled(void);
INT_32 ssp_busy(void); 
INT_32 ssp_receive_fifo_full(void);
INT_32 ssp_receive_fifo_not_empty(void);
INT_32 ssp_transmit_fifo_not_full(void);
INT_32 ssp_transmit_fifo_empty(void);
INT_32 ssp_loopback_is_on(void);
INT_32 ssp_int_transmit_idle_enabled(void);
INT_32 ssp_int_receive_overflow_enabled(void);
INT_32 ssp_int_receive_enabled(void);
INT_32 ssp_int_transmit_enabled(void);
INT_32 ssp_spi_spo_is_set(void);
INT_32 ssp_spi_sph_is_set(void);
void ssp_clr_receive_overflow(void);
INT_32 ssp_int_transmit_idle(void);
INT_32 ssp_int_transmit(void);
INT_32 ssp_int_receive(void);
INT_32 ssp_int_receive_overflow(void);

#endif