sma_coreutils.c

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/***********************************************************************
 * $Workfile:   SMA_coreutils.c  $
 * $Revision:   1.0  $
 * $Author:   MaysR  $
 * $Date:   Aug 09 2002 10:17:54  $
 *
 * Project:
 *
 * Description: This file contains functions that interact directly 
 *  with the ARM core.  These functions include:
 * 
 *  SMA_core_irq: A function that programs the IRQ bit of the CPSR to
 *                the state indicated by the parameter.  It returns
 *                the previous state of the IRQ bit.
 * 
 *  SMA_core_fiq: A function that programs the FIQ bit of the CPSR to
 *                the state indicated by the parameter.  It returns
 *                the previous state of the FIQ bit.
 * 
 *
 * Revision History:
 * $Log:   //smaicnt2/pvcs/VM/CHIPS/archives/SOC/Source/SMA_coreutils.c-arc  $
 * 
 *    Rev 1.0   Aug 09 2002 10:17:54   MaysR
 * Initial revision.
 * 
 ***********************************************************************
 * 
 *  Copyright (c) 2002 Sharp Microelectronics of the Americas
 *
 *  All rights reserved
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 *  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 *  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
 *  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
 *  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
 *  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT.  USE OF THIS SOURCE
 *  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 **********************************************************************/

#include "SMA_coreutils.h"

/***********************************************************************
 * Function: SMA_core_irq
 *
 * Purpose: Enable or disable the IRQ bit in the CPSR
 * 
 * Processing:  Test the current mode, if it is the same, return.  
 *              Otherwise, set the new mode, and return the old mode.
 *
 * Parameters:  irq_state: new IRQ state to set CPSR to.
 *
 * Outputs:  None
 *
 * Returns:  INT_STATE: previous state of the IRQ bit.
 *
 * Notes:  You can not change the control bits of the CPSR from USER 
 *         mode or from Thumb mode.  Do not call this function from 
 *         either of these modes.
 *
 **********************************************************************/
CORE_INT_STATE SMA_core_irq(CORE_INT_STATE irq_state)
{
    UNS_32 tmp, ret;

    __asm
    {
        MRS     ret, CPSR                 // get return value
        MRS     tmp, CPSR                 // get current status register
        BIC     tmp, tmp, #ARM_IRQ        // clear the IRQ bit
        ORR     tmp, tmp, irq_state, LSL #7 // set IRQ bit per param
        MSR     CPSR_c, tmp               // write status register
        MOV     irq_state, ret, LSR #7    // shift return value
        AND     irq_state, irq_state, #1  // mask all but bit zero
    }
    return irq_state;
}

/***********************************************************************
 * Function: SMA_core_fiq
 *
 * Purpose: Enable or disable the FIQ bit in the CPSR
 * 
 * Processing:  Test the current mode, if it is the same, return.  
 *              Otherwise, set the new mode, and return the old mode.
 *
 * Parameters:  fiq_state: new FIQ state to set CPSR to.
 *
 * Outputs:  None
 *
 * Returns:  INT_STATE: previous state of the FIQ bit.
 *
 * Notes:  You can not change the control bits of the CPSR from USER 
 *         mode or from Thumb mode.  Do not call this function from 
 *         either of these modes.
 *
 **********************************************************************/
CORE_INT_STATE SMA_core_fiq(CORE_INT_STATE fiq_state)
{
    UNS_32 tmp, ret;

    __asm
    {
        MRS     ret, CPSR                 // get return value
        MRS     tmp, CPSR                 // get current status register
        BIC     tmp, tmp, #ARM_FIQ        // clear the FIQ bit
        ORR     tmp, tmp, fiq_state, LSL #6 // set FIQ bit per param
        MSR     CPSR_c, tmp               // write status register
        MOV     fiq_state, ret, LSR #6    // shift return value
        AND     fiq_state, fiq_state, #1  // mask all but bit zero
    }
    return fiq_state;
}