lh7a400_mmc.h

sharp的arm920t 7A400的评估板附带光盘Sharp KEVLH7A400 v0.3b Welcome to the SHARP KEV7A400 Evaluation board

/**********************************************************************
 *  $Workfile:   LH7A400_mmc.h  $
 *  $Revision:   1.2  $
 *  $Author:   MaysR  $
 *  $Date:   Jun 20 2002 10:45:28  $
 *
 *	Project: LH7A400 headers
 *
 *	Description:
 *      This file contains the structure definitions and manifest
 *      constants for LH7A400 component:
 *          Multi-Media Card / Secure Digital card
 *
 *	References:
 *		(1) Sharp LH7A400 Universal SoC User's Guide
 *
 *	Revision History:
 *  $Log:   //smaicnt2/pvcs/VM/CHIPS/archives/SOC/LH7A400/Processor/LH7A400_mmc.h-arc  $
 * 
 *    Rev 1.2   Jun 20 2002 10:45:28   MaysR
 * Removed rouge semi-colons
 * 
 *    Rev 1.1   Jun 19 2002 17:44:34   MaysR
 * Added missing end parentheses.
 * 
 *    Rev 1.0   Jun 19 2002 14:37:20   MaysR
 * Initial revision.
 * 
 * 
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 *	COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *		CAMAS, WA
 *********************************************************************/

#ifndef LH7A400_MMC_H
#define LH7A400_MMC_H

#include "SMA_types.h"

/* MMC Register Structure */ 

typedef struct 
{
    volatile UNS_32   str_stp_clk;   /* Clock control register */ 
    volatile UNS_32   mmc_status;    /* Controller status register */ 
    volatile UNS_32   mmc_clk_rate;  /* MMC clock divider register */
    volatile UNS_32   mmc_prediv;    /* MMC clock pre-divider register */
    volatile UNS_32   spi_mode;      /* SPI mode control register */
    volatile UNS_32   cmd_data_cont; /* Command control register */
    volatile UNS_32   response_to;   /* Response timeout register */
    volatile UNS_32   read_to;       /* Read timeout register */
    volatile UNS_32   block_len;     /* Block length register */
    volatile UNS_32   number_blks;   /* Number of blocks register */ 
    volatile UNS_32   int_status;    /* Interrupt status register */
    volatile UNS_32   eoi_reg;       /* End Of Interrupt register */ 
    volatile UNS_32   reserved1;     /* 0x130 */
    volatile UNS_32   int_mask;      /* Interrupt mask register */
    volatile UNS_32   cmd_num;       /* Command Number register */
    volatile UNS_32   argument;      /* Command Argument register */
    volatile UNS_32   result_fifo;   /* Result FIFO location */
    volatile UNS_32   reserved2;     /* 0x144 */
    volatile UNS_32   data_fifo;     /* Data FIFO register */
    volatile UNS_32   buf_part_full; /* Partial buf for stream mode */
} MMCREGS;

/**********************************************************************
 * Clock Control Register Bit Fields
 *********************************************************************/ 
#define MMC_STOP_CLK                _BIT(0)
#define MMC_START_CLK               _BIT(1)

/**********************************************************************
 * Controller Status Register Bit Fields
 *********************************************************************/ 
#define MMC_TIME_OUT_READ           _BIT(0)
#define MMC_TIME_OUT_RESONSE        _BIT(1)
#define MMC_CRC_WRITE_ERROR         _BIT(2)
#define MMC_CRC_READ_ERROR          _BIT(3)
#define MMC_SPI_READ_ERROR_TOKEN    _BIT(4)
#define MMC_RESPONSE_CRC_ERROR      _BIT(5)
#define MMC_FIFO_EMPTY              _BIT(6)
#define MMC_FIFO_FULL               _BIT(7)
#define MMC_CLK_ENABLE              _BIT(8)
// #define MMC_WRITE_EN_DIFF           _BIT(9)
// #define MMC_RES_ERROR_DIFF          _BIT(10)
#define MMC_DATA_TRAN_DONE          _BIT(11)
#define MMC_PRG_RW_DONE             _BIT(12)
#define MMC_END_CMD_RESP            _BIT(13)

/**********************************************************************
 * Clock Rate Register Bit Fields
 *********************************************************************/ 
#define MMC_CLK_RATE(n)             _SBF(0, (n & 0x7))

/**********************************************************************
 * MMC Clock Pre-divider Register Bit Fields
 *********************************************************************/ 
#define MMC_PREDIV(n)               _SBF(0, (n & 0xF))
#define MMC_EN                      _BIT(4)
#define MMC_APB_RD_EN               _BIT(5)

/**********************************************************************
 * SPI Register Bit Fields
 *********************************************************************/ 
#define MMC_SPI_EN                  _BIT(0)
#define MMC_CRC_ON                  _BIT(1)
#define MMC_SPI_CS_EN               _BIT(2)
#define MMC_SPI_CS_ADDR             _BIT(3)

/**********************************************************************
 * Command Data Control Register Bit Fields
 *********************************************************************/ 
#define MMC_REPONSE_FORMAT(n)       _SBF(0, (n & 0x3))
#define MMC_DATA_EN                 _BIT(2)
#define MMC_WRITE                   _BIT(3)
#define MMC_STREAM                  _BIT(4)
#define MMC_BUSY                    _BIT(5)
#define MMC_INITIALIZE              _BIT(6)

/**********************************************************************
 * Reset Time Out Register Bit Fields
 *********************************************************************/ 
#define MMC_RESET_TO(n)             _SBF(0, (n & 0xFF))

/**********************************************************************
 * Read Time Out Register Bit Fields
 *********************************************************************/ 
#define MMC_READ_TO(n)              _SBF(0, (n & 0xFFFF))

/**********************************************************************
 * Block Length Register Bit Fields
 *********************************************************************/ 
#define MMC_BLOCK_LEN(n)            _SBF(0, (n & 0x3FF))

/**********************************************************************
 * Number Of Blocks Register Bit Fields
 *********************************************************************/ 
#define MMC_NOB(n)                  _SBF(0, (n & 0xFFFF))

/**********************************************************************
 * Interrupt Mask, Status, & End Of Interrupt Register Bit Fields
 *********************************************************************/ 
#define MMC_DATA_TRAN               _BIT(0)
#define MMC_PRG_DONE                _BIT(1)
#define MMC_END_CMD                 _BIT(2)
#define MMC_BUF_READY               _BIT(3)
#define MMC_BUS_CLK_STOPPED         _BIT(4)
                                          
/**********************************************************************
 * Command Number Register Bit Field
 *********************************************************************/ 
#define MMC_CMD_NUM(n)              _SBF(0, (n & 0x3F))

/**********************************************************************
 * Response & Data FIFO Register Bit Fields
 *********************************************************************/ 
#define MMC_RES_DATA_FIFO(n)        _SBF(0, (n & 0xFFFF))

/**********************************************************************
 * Buffer Part Full Register Bit Field
 *********************************************************************/ 
#define MMC_BUF_PART_FULL           _BIT(0)


#endif /* LH7A400_MMC_H */