lh7a400_mmu.i

sharp的arm920t 7A400的评估板附带光盘Sharp KEVLH7A400 v0.3b Welcome to the SHARP KEV7A400 Evaluation board

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; $Workfile:   LH7A400_mmu.i  $
; $Revision:   1.2  $
; $Author:   BarnettH  $
; $Date:   May 31 2002 15:48:00  $
;
; Project:  LH7A400
;
; Description:
;   LH7A400 MMU coprocessor definitions
;   (ARM assembly language include file)
; 
; Notes:
;   (1) MCR/MRC{cond} P15, opcode_1, Rd, CRn, CRm, opcode_2
;
; References:
;   (1) ARM922T Technical Reference Manual, ARM DDI 0184B.
;
; $Log:   //smaicnt2/pvcs/VM/CHIPS/archives/SOC/LH7A400/Processor/LH7A400_mmu.i-arc  $
;
;   Rev 1.2   May 31 2002 15:48:00   BarnettH
;Added MMU_CONTROL_B bit
;
;   Rev 1.1   May 08 2002 14:54:08   BarnettH
;Added Clocking Mode Bit Field per Table 2-11
;
;   Rev 1.0   Apr 11 2002 11:23:10   BarnettH
;Initial revision.
;
; SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
; OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
; AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
; SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
;
; SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
; FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
; SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
; FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
;
; COPYRIGHT (C) 2001  SHARP MICROELECTRONICS OF THE AMERICAS INC.
;                        CAMAS, WA
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; MMU, Coprocessor Definitions
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SYS_CONTROL_CP    CP 15
MMU_CP            CP 15
CACHE_CP          CP 15

; Valid CP15 registers
MMU_REG_ID           CN 0
MMU_REG_CACHE_TYPE   CN 0
MMU_REG_CONTROL      CN 1
MMU_REG_TTB          CN 2  ; Translation Table Base Address
MMU_REG_DAC          CN 3  ; Domain Access Control
MMU_REG_FS           CN 5  ; Fault Status
MMU_REG_FA           CN 6  ; Fault Address
MMU_REG_CACHE_OP     CN 7  ; Cache Operations
MMU_REG_TLB_OP       CN 8  ; Translation Lookaside Buffer Operation
MMU_REG_CACHE_LOCK   CN 9  ; Cache Lockdown
MMU_REG_TLB_LOCK     CN 10 ; TLB Lockdown
MMU_REG_FCSE_PID     CN 13 ; Fast Context Switch Extension

; Control register bits
MMU_CONTROL_M        EQU (1 << 0)   ; MMU Enable
MMU_CONTROL_A        EQU (1 << 1)   ; Alignment Fault
MMU_CONTROL_C        EQU (1 << 2)   ; Data Cache
MMU_CONTROL_B        EQU (1 << 7)   ; Endianess
MMU_CONTROL_S        EQU (1 << 8)   ; System Protection
MMU_CONTROL_R        EQU (1 << 9)   ; ROM Protection
MMU_CONTROL_I        EQU (1 << 12)  ; Instruction Cache
MMU_CONTROL_V        EQU (1 << 13)  ; Exception Vector location
MMU_CONTROL_RR       EQU (1 << 14)  ; Round Robin Replacement
MMU_CONTROL_NF       EQU (1 << 30)  ; Not FastBus
MMU_CONTROL_IA       EQU (1 << 31)  ; Asynchronous Clock Select
; Clocking Mode Bit Field per Table 2-11
MMU_CONTROL_FASTBUS_CLOCK  EQU (0)
MMU_CONTROL_SYNCH_CLOCK    EQU (MMU_CONTROL_NF)
MMU_CONTROL_ASYNCH_CLOCK   EQU (MMU_CONTROL_IA :OR: MMU_CONTROL_NF)

; Convenient EQU's
MMU_ENABLE              EQU (MMU_CONTROL_M)
MMU_ENABLE_CACHE        EQU (MMU_CONTROL_M :OR: \
                             MMU_CONTROL_C :OR: MMU_CONTROL_I)
MMU_CONTROL_ALL_BITS    EQU (MMU_CONTROL_M :OR: MMU_CONTROL_A :OR: \
                             MMU_CONTROL_C :OR: MMU_CONTROL_B :OR: \
                             MMU_CONTROL_S :OR: MMU_CONTROL_R :OR: \
                             MMU_CONTROL_I :OR: MMU_CONTROL_V :OR: \
                             MMU_CONTROL_RR :OR: \
                             MMU_CONTROL_NF :OR: MMU_CONTROL_IA)

; Small page size - 4KB
; Large page size - 64KB
; Section size - 1MB
SMALL_PAGE_SIZE      EQU      (0x400 * 4)
LARGE_PAGE_SIZE      EQU      (0x4000 * 4)
SECTION_SIZE         EQU      (0x40000 * 4)

; Small page tables and Large page tables are the same size,
; 1024 bytes or 256 entries
; Large page tables have each of 16 entries replicated 16 times
; in succeeding memory locations
PAGE_TABLE_SIZE      EQU      (0x100 * 4) ; 256 entries
TRANS_TABLE_SIZE     EQU      (0x1000 * 4); 4096 entries

; N.B.: Translation table must be based on a 16KB boundary.
;       Page tables must be based on 1KB boundaries.

   END