lh7a400_evbstart.s

sharp的arm920t 7A400的评估板附带光盘Sharp KEVLH7A400 v0.3b Welcome to the SHARP KEV7A400 Evaluation board

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; * $Workfile:   LH7A400_evbstart.s  $
; * $Revision:   1.0  $
; * $Author:   WellsK  $
; * $Date:   Sep 23 2002 13:52:02  $
; *
; * Project:  LH7A400 Evaluation Board
; *
; * Description:
;       BootROM code for LH7A400
;
;Pre-defines:  See also LH7A400_evb.i
;   START_C_ENTRY
;   If it is desired to use this startup to jump to C Runtime
;       initialization code,  pre-define START_C_ENTRY
;   with an assembler SETA pre-define,e.g., "START_C_ENTRY SETA 0x1"
;   Otherwise, this code will run, then spin while waiting
;   for the debugger to interrupt it.
;
;   BOOTMODE = 1
;   Maps Asynchronous Flash to 0x0, Synchronous Flash to 0xF0000000
;   Any other value swaps mapping.
;
;
; * $Log:   //smaicnt2/pvcs/VM/CDROM/archives/KEV7A400/Software/Startup_lite/LH7A400_evbstart.s-arc  $
; 
;    Rev 1.0   Sep 23 2002 13:52:02   WellsK
; Initial revision.
; 
;    Rev 1.0   Sep 14 2002 11:38:06   WellsK
; Initial revision.
; 
;    Rev 1.11   Jun 27 2002 09:37:22   BarnettH
; Allocated space for later installation of FIQ Handler, so default handlers will remain in effect.
; 
;
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;  
;   Copyright (c) 2002 Sharp Microelectronics of the Americas
; 
;   All rights reserved
; 
;   SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
;   OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
;   AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
;   SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
; 
;   SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
;   FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
;   SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT.  USE OF THIS SOURCE
;   FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
; 
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    AREA    BootEVB400, CODE    ; name this block of code
    
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; KEV7A400 Definitions
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; See LH7A400_evb.i

    INCLUDE LH7A400_evb.i
    
;    IMPORT  LH7A400_clkset_default
    IMPORT  LH7A400_clock_set
    IMPORT  LH7A400_delay_timer_msecs
    IMPORT  LH7A400_evb_get_dipsw
    IMPORT  LH7A400_evb_set_led
    IMPORT  LH7A400_evb_toggle_led
    IMPORT  LH7A400_init_mem
    IMPORT  LH7A400_init_mmu_tables_wrapper
    IMPORT  LH7A400_init_muxdpins
    IMPORT  SMA_copylongs
    IMPORT  SMA_get_mmu_control_reg
    IMPORT  util_set_sevenseg_blank
    IMPORT  util_set_sevenseg_hexval
    IMPORT	default_clock

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;*********** The RESET entry point ***********
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    EXPORT  Rom_Start
    ENTRY
    ; Exception vector table
Rom_Start
    ; run out of the ROM Physical location
    LDR     pc, L_Reset_Handler ; 0x00
    B       Undefined_Handler   ; 0x04
    B       SWI_Handler         ; 0x08
    B       Prefetch_Handler    ; 0x0C
    B       Abort_Handler       ; 0x10
    NOP                         ; Reserved vector
    B       IRQ_Handler         ; 0x18
FIQ_Handler
    ; FIQ code can grow from here up to space allocated maximum
    SUBS     pc,lr,#4           ; 0x1C
    
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; Allocate space for the FIQ Handler, if used.
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    SPACE   0x100 - 0x20
    ALIGN   

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; The following handlers save status if possible running from flash
; See Save_Status comments for locations in IRAM of saved status.
; User will replace these under program control as desired when
; Exception Vector Table is in RAM.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

L_Reset_Handler
    DCD     Reset_Handler

Undefined_Handler
    B       Save_Status

SWI_Handler
    B       Save_Status
    
Prefetch_Handler
    B       Save_Status
    
Abort_Handler
    B       Save_Status
    
IRQ_Handler
    B       Save_Status
    
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; Reset Handler 
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Reset_Handler
    ; Ensure MMU disabled, all control bits cleared, FastBus Mode.
    MOV     r1,#0
    MRC     MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
    LDR     r2,=(MMU_CONTROL_ALL_BITS)
    BIC     r1, r1, r2
    MCR     MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0

    ; Flush the TLB and Caches
    MVN     r1,#0
    ; Flush the TLB
    MCR     MMU_CP, 0, r1, MMU_REG_TLB_OP, c7, 0
    ; Invalidate both I and D Cache
    MCR     MMU_CP, 0, r1, MMU_REG_CACHE_OP, c7, 0

; Save Boot Status in both Boot Type and Software Reset Type locations
; See LHA400_evb.i for addresses in IRAM where these data are stored
; for later reference if needed.
save_boot_status
    LDR     r1,=CLKSC_PWRSR
    LDR     r2,=BOOT_STATUS_STORE_ADDR 
    LDR     r3,[r1]
    STR     r3,[r2]
    LDR     r2,=SRVAL_STATUS_STORE_ADDR 
    STR     r3,[r2] 
    
; Clear the SAVE_STATUS area to ensure no artifacts on a fault
clear_save_status
    MOV     r0,#0
    LDR     r1,=0x80
    LDR     r2,=SAVE_STATUS_STORE_ADDR
    SUB     r2, r2, #4
80
    STR     r0, [r2], #-4
    SUBS    r1, r1, #4
    BGT     %B80
81
    
check_for_no_init
    MOV     r0, #CPU_DIP_SWITCH
    BL      LH7A400_evb_get_dipsw
    BIC     r0, r0, #(CPLD_CPUDIPSW_DCACHE_BIT :OR: \
                      CPLD_CPUDIPSW_ICACHE_BIT)
    CMP     r0, #CPLD_CPUDIPSW_NO_INIT_RUN
    BNE     Normal_Start
    B       .

Normal_Start
; Enable I-Cache immediately
    MRC     MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
    ORR     r1, r1, #MMU_CONTROL_I
    MCR     MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
    
; After Reset, the processor begins execution in ARM Supervisor Mode
; with interrupts disabled.  However, the processor may be in another
; mode when it arrives here, e.g., a branch directly to 0x0 while in
; System Mode.
;

; Enter SVC mode, ARM Mode, mask interrupts at core, clear status bits
init_CPU_mode
    MOV     r0,#MODE_SVC:OR:I_MASK:OR:F_MASK ; No Interrupts
    MSR     cpsr_cxsf, r0

; Reset the SVC stack pointer to Internal SRAM
init_SVC_stack
    LDR     r13, =IRAM_SVC_STACK_BASE
    
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; Since we now have a stack, we can do basic initialization with C code
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; Initialize Multiplexed pins
init_mux_pins
    BL      LH7A400_init_muxdpins
    
; Initialize the Clocks
init_clock
    LDR     r0, =default_clock
    LDR     r0, [r0]
    BL      LH7A400_clock_set
    
; Initialize SDRAM and SRAM memory
init_memory
    BL      LH7A400_init_mem
    
; Watchdog Timer cannot be stopped, but it can be masked
; Ensure all interrupts are masked, including WDT interrupts
mask_interrupts
    MVN     r0,#0
    LDR     r1,=INTC_REG_BASE
    STR     r0,[r1,#INTC_INTENC_OFFSET]
    
; Enter SVC mode, ARM Mode, no interrupts, clear status bits
reset_CPU_mode
    MOV     r0,#(MODE_SVC:OR:I_MASK:OR:F_MASK) ; No Interrupts
    MSR     cpsr_cxsf, r0
; Reset the SVC stack pointer to Internal SRAM
reset_SVC_stack
    LDR     r13, =IRAM_SVC_STACK_BASE
    
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;; Initialize Regions
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    IMPORT  |Image$$ER_RO$$Length|
    IMPORT  |Image$$ER_RO$$Base|
    IMPORT  |Image$$ER_RW$$Length|
    IMPORT  |Load$$ER_RW$$Base|
    IMPORT  |Image$$ER_RW$$Base|
    IMPORT  |Image$$ER_ZI$$ZI$$Length|
    IMPORT  |Image$$ER_ZI$$ZI$$Base|

init_regions
; zzz Revisit this conditional assembly
    IF :DEF: IRAMATZERO
          IF IRAMATZERO = {TRUE}
    LDR   R4, =IRAM_PHYS_BASE
          ELSE
    LDR   r4, =SDRAM0_PHYS_BASE  ; This assumes SDRAM is mapped to 0x0
          ENDIF
    ELSE
    LDR   r4, =SDRAM0_PHYS_BASE  ; This assumes SDRAM is mapped to 0x0
    ENDIF

; Set up the .text section in RAM
init_text
    LDR     r0, =|Image$$ER_RO$$Length|
    LDR     r1, =|Image$$ER_RO$$Base|
    MOV     r2, r4
    BL      SMA_copylongs
    
; Set up the .data section in RAM
init_data
    LDR     r0, =|Image$$ER_RW$$Length|
    LDR     r1, =|Load$$ER_RW$$Base|
    LDR     r2, =|Image$$ER_RW$$Base|
    LDR     r3, =Rom_Start
    SUB     r2, r2, r3
    ADD     r2, r2, r4
    BL      SMA_copylongs
    
; Zero Initialize .bss section in RAM
init_zi
    LDR     r0, =|Image$$ER_ZI$$ZI$$Length|
    CMP     r0, #0
    BEQ     %F91
    MOV     r1, #0
    LDR     r2, =|Image$$ER_ZI$$ZI$$Base|
    LDR     r3, =Rom_Start
    SUB     r2, r2, r3
    ADD     r2, r2, r4
90
    STR     r1, [r2], #4
    SUBS    r0, r0, #4
    BGT     %B90