lh7a400_flashdl.s

sharp的arm920t 7A400的评估板附带光盘Sharp KEVLH7A400 v0.3b Welcome to the SHARP KEV7A400 Evaluation board

;***********************************************************************
; * $Workfile:   LH7A400_flashdl.s  $
; * $Revision:   1.0  $
; * $Author:   WellsK  $
; * $Date:   Sep 23 2002 13:52:04  $
; *
; * Project:  LH7A400 Evaluation Board
; *
; * Description:
;       Barebones initialization code to prepare for Flash download.
;
;	Pre-defines: 
;  		BOOTMODE
;			Pre-define BOOTMODE SETA 1 to set Boot from Asynch Flash
;			Otherwise, Boot will be assumed to be Synch Flash
;
; * $Log:   //smaicnt2/pvcs/VM/CDROM/archives/KEV7A400/Software/Startup_lite/LH7A400_flashdl.s-arc  $
; 
;    Rev 1.0   Sep 23 2002 13:52:04   WellsK
; Initial revision.
; 
;    Rev 1.0   Sep 14 2002 11:38:08   WellsK
; Initial revision.
; 
;    Rev 1.4   Jun 13 2002 18:56:56   BarnettH
; Removed superfluous code. Adapted to new clock_set design.
; 
;    Rev 1.3   Jun 06 2002 18:04:08   BarnettH
; Deleted much unneeded code and comments.  No changes to required functionality.
; 
;    Rev 1.2   Nov 14 2001 15:54:20   BarnettH
; Changed CS1 to 16-bit mode
; 
;    Rev 1.1   Nov 13 2001 08:35:40   BarnettH
; Changed comments
; 
;    Rev 1.0   Sep 19 2001 19:51:28   BarnettH
; Initial revision.
; 
; *  COPYRIGHT (C) 2001  SHARP MICROELECTRONICS OF THE AMERICAS INC.
; *                         CAMAS, WA
;**********************************************************************/
;

	AREA 	BootEVB400, CODE 	; name this block of code

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; Board Definitions
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	INCLUDE	LH7A400_evb.i

	IMPORT	LH7A400_clkset_default
	IMPORT	LH7A400_clock_set
	IMPORT	LH7A400_delay_timer_msecs
	IMPORT	LH7A400_evb_toggle_led
	IMPORT	LH7A400_init_mem
	IMPORT	util_set_sevenseg_hexval

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; Begin executable code
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

    ENTRY
    EXPORT  Start
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Start
; Ensure MMU is disabled and all control bits are cleared.
; Enable I-Cache immediately
	EOR		r1,r1,r1
	MRC		MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
	LDR		r2,=(MMU_CONTROL_ALL_BITS)
	BIC		r1, r1, r2
	LDR		r2, =MMU_CONTROL_I
	ORR		r1, r1, r2
	MCR		MMU_CP, 0, r1, MMU_REG_CONTROL, c0, 0
;  Flush TLB
	MOV		r1,#0
	MCR		MMU_CP, 0, r1, MMU_REG_TLB_OP, c7, 0
;  Invalidate ID Cache
	MOV		r1,#0
	MCR		MMU_CP, 0, r1, MMU_REG_CACHE_OP, c7, 0
	NOP
	NOP
	NOP
	NOP
	NOP

init_SVC_stack
; Enter SVC mode and setup the SVC stack pointer in Internal SRAM
    MOV     r0,#MODE_SVC:OR:I_MASK:OR:F_MASK ; No Interrupts
    MSR     cpsr_cxsf, r0
    LDR     r13, =IRAM_SVC_STACK_BASE
    
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Since we have a stack, we can do some basic initialization from 'C'
; We can initialize memory from 'C' while we are running out of Flash
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

; Initialize the Clocks
init_clock
	; Set up clock speed argument
    LDR     r0, =LH7A400_clkset_default
    LDR     r0, [r0]
    BL      LH7A400_clock_set

init_memory
	; Set up clock speed argument again before call to init_mem
	BL		LH7A400_init_mem

; revise the SMC BCR0 and BCR1
; This sets it up for SW7 position 3 programming.
init_bcrx
	LDR		r0,=0x80002000
	LDR		r1,=0x1000FBEF
	LDR		r2,=0x1000FBEF ; 16-bit SRAM
	;LDR		r2,=0x2000FBEF ; 32-bit SRAM
	STR		r1,[r0,#4]
	STR		r2,[r0,#0]

; Clear the SAVE_STATUS area to ensure no artifacts on a fault
clear_save_status
	EOR		r0,r0,r0
	LDR		r1,=0x80
	LDR		r2,=SAVE_STATUS_STORE_ADDR
	SUB		r2, r2, #4
80
	STR		r0, [r2], #-4
	SUBS	r1, r1, #4
	BGT		%B80
81

; Enter SVC mode, ARM Mode, no interrupts,
; and reset the SVC stack pointer in Internal SRAM
    MOV     r0,#(MODE_SVC:OR:I_MASK:OR:F_MASK) ; No Interrupts
    MSR     cpsr_cxsf, r0
    LDR     r13, =IRAM_SVC_STACK_BASE
;
; Now we sit and spin with interrupts disabled and SP at top
;
idle_sitnspin
	MOV		r5, #0
	LDR		r7, = 0xFFFFFF00
	; r8 holds simple 32-bit activity counter
	MOV		r8, #0
36
	ADD		r5, r5, #1
	BIC		r5, r5, r7
	MOV		r0, r5
	MOV		r1, #0
	BL		util_set_sevenseg_hexval
	MOV		r0, #100		; ~1/10 second
	BL		LH7A400_delay_timer_msecs
	ADD		r8, r8, #1
	b		%B36

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Dummy Area to prevent link to C runtime lib
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	EXPORT  __main	; defined to ensure C runtime lib is not linked in
__main				; defined to ensure C runtime lib is not linked in

; sets up BCR's when EVB SW7 is in position 1 (Flash is boot device)
setupflashdl1
	LDR		r0,=0x80002000
	LDR		r1,=0x1000FBEF
	LDR		r2,=0x2000FBEF
	STR		r1,[r0,#0]
	STR		r2,[r0,#4]
	B		.

; sets up BCR's when EVB SW7 is in position 3 (SRAM is boot device)
setupflashdl3
	LDR		r0,=0x80002000
	LDR		r1,=0x1000FBEF
	LDR		r2,=0x2000FBEF
	STR		r1,[r0,#4]
	STR		r2,[r0,#0]
	B		.

BootROM_Limit
    END