lh7a400_evbmmuinit.h

sharp的arm920t 7A400的评估板附带光盘Sharp KEVLH7A400 v0.3b Welcome to the SHARP KEV7A400 Evaluation board

/**********************************************************************
 *  $Workfile:   LH7A400_evbmmuinit.h  $
 *  $Revision:   1.0  $
 *  $Author:   WellsK  $
 *  $Date:   Sep 23 2002 13:52:02  $
 *
 *  Project: LH7A400 Evaluation Board
 *
 *  Description:
 *      This file contains the following information for the
 *      LH7A400 Evaluation board:
 *
 *      Typedefs for types for initializing the MMU
 *      Manifest constants for selecting definition of
 *          MMU_LEVEL1_DESCRIPTORS
 *      Prototypes for functions for initializing the MMU
 *
 * Notes:
 *    (1) Non-standard line length is used in this file to permit
 *          #define constants to be on a single line for readability.
 *
 *  Revision History:
 *  $Log:   //smaicnt2/pvcs/VM/CDROM/archives/KEV7A400/Software/Startup_lite/LH7A400_evbmmuinit.h-arc  $
 * 
 *    Rev 1.0   Sep 23 2002 13:52:02   WellsK
 * Initial revision.
 * 
 *    Rev 1.0   Sep 14 2002 11:38:06   WellsK
 * Initial revision.
 * 
 *    Rev 1.9   Aug 12 2002 15:09:56   BarnettH
 * Cleaned up banner.
 * Cleaned up bracing.
 * Added justification for long lines.
 * 
 *    Rev 1.8   Jun 05 2002 11:00:40   BarnettH
 * Changed #includes to only LH7A400_evb.h
 * Moved all constant data to LH7A400_evbmmuinit_data.c
 * 
 *    Rev 1.7   Apr 11 2002 17:23:12   BarnettH
 * Changed processor name to standard
 * Removed tabs.
 * 
 *    Rev 1.6   Mar 13 2002 11:24:18   wellsk
 * Corrected MMU table for tt_cached_sdram_at_0. Added
 * MMU entries for CompactFLASH.
 * 
 *    Rev 1.5   Nov 30 2001 11:23:58   WellsK
 * Added MMU initialization block for
 * SDRAM cached at 0x0 and uncached
 * at 0xC0000000.
 * 
 *    Rev 1.4   Nov 29 2001 11:30:24   SuryanG
 * Updated comments.
 * 
 *    Rev 1.3   Nov 29 2001 11:26:00   SuryanG
 * Added MMU mapping for Ethernet Controller.
 * Converted to SMA_types.
 * 
 *    Rev 1.2   Nov 15 2001 11:37:26   MaysR
 * Added additional MMU configuration tables for LCD testing.
 *
 *    Rev 1.1   Nov 02 2001 09:16:12   MaysR
 * Corrected MMU translation tables to reflect fragmented SDRAM memory
 * on Aruba EVB.  Added additional table with SDRAM chip select memory
 * space configured wide open for testing.
 *
 *    Rev 1.0   Sep 18 2001 18:04:06   BarnettH
 * Initial revision.
 *
 ***********************************************************************
 * 
 *  Copyright (c) 2002 Sharp Microelectronics of the Americas
 *
 *  All rights reserved
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 *  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 *  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
 *  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
 *  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
 *  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT.  USE OF THIS SOURCE
 *  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 **********************************************************************/

#ifndef LH7A400_EVBMMUINIT_H
#define LH7A400_EVBMMUINIT_H

#include "LH7A400_evb.h"

/**********************************************************************
 * LH7A400 EVB MMU Initialization typedefs
 *********************************************************************/

typedef struct
{
        UNS_32 vidx[TT_ENTRIES];
} TRANSTABLE;

typedef struct
{
        UNS_32 vidx[PT_ENTRIES];
} PAGETABLE;

/*
 * UNS_32 num_sections: number of sections >=1 for all blocks
 *                            except last; last = 0
 * UNS_32 virt_addr: as required, base Virtual address for block
 * UNS_32 phys_addr: as required, PT address or Section address
 * UNS_32 entry is composed of the following 'or'd' together:
 *  access_perm:  L1D_AP_x (x = SVC_ONLY, USR_RO, ALL)
 *  domain:   L1D_DOMAIN(n) as applicable
 *  cacheable:  L1D_CACHEABLE if applicable
 *  write_buffered:  L1D_BUFFERABLE if applicable
 *  descriptor_type: L1D_TYPE_x (x = FAULT, PAGE, SECTION)
 *
 */
typedef const struct
{
    UNS_32 num_sections;
    UNS_32 virt_addr; /* calculate index from this */
    UNS_32 phys_addr; /* initialize location @ index w/this */
    UNS_32 entry; /* 'or'd' combinations of entry settings;
                               'or' this with phys_addr */
    /*  Entry settings:
    access_perm, domain, cacheable, write_buffered, descriptor_type
    */
} TT_SECTION_BLOCK;

typedef const struct
{
    UNS_32    num_sections;
    UNS_32    virt_addr; /* calculate index from this */ 
    UNS_32    phys_addr; /* initialize location @ index w/this */
    UNS_32    entry;  /* 'or'd' combinations of entry settings;
                               'or' this with phys_addr */ 
    /*  Entry settings:
    access_perm, domain, cacheable, write_buffered, descriptor_type
    */ 
} PT_PAGE_BLOCK;
 
/***********************************************************************
 * Identify which MMU Translation Table initialization data to use
 * Data are in LH79520_evbmmuinit_data.c
 * Both MMU_LEVEL1_INIT and a specific map from the MMU_MAP_xxxx
 * #defines below should be defined by the user.  If no specific map is
 * selected by a pre-define, SDRAM is based at 0x0 by default if
 * MMU_LEVEL1_INIT is defined.
 **********************************************************************/

#if !defined MMU_LEVEL1_INIT

#error MMU_LEVEL1_INIT must be defined to select MMU Table at startup

#else

/* If MMU_LEVEL1_INIT is defined, then set up the default map */ 
#if !defined (MMU_MAP_BASIC)
#define MMU_MAP_BASIC
#endif

#endif

/* SDRAM at 0x0, default map */ 

#if defined (MMU_MAP_BASIC)

extern TT_SECTION_BLOCK tt_init_basic [];
#undef MMU_LEVEL1_DESCRIPTORS
#define MMU_LEVEL1_DESCRIPTORS  ((TT_SECTION_BLOCK *) tt_init_basic)

#endif

/* SRAM at 0x0 */ 

#if defined (MMU_MAP_SRAM_0)

extern TT_SECTION_BLOCK tt_init_sram_at_0 [];
#undef MMU_LEVEL1_DESCRIPTORS
#define MMU_LEVEL1_DESCRIPTORS  ((TT_SECTION_BLOCK *) tt_init_sram_at_0)
#undef MMU_MAP_BASIC

#endif

/* SRAM at 0x0, SDRAM alternate mapping */ 

#if defined (MMU_MAP_SDRAM_OPEN_SRAM_0)

extern TT_SECTION_BLOCK tt_sdram_open_sram_at_0 [];
#undef MMU_LEVEL1_DESCRIPTORS
// Long line for readability
#define MMU_LEVEL1_DESCRIPTORS  ((TT_SECTION_BLOCK *) tt_sdram_open_sram_at_0)
#undef MMU_MAP_BASIC

#endif

/* IRAM at 0x0, SDRAM alternate mapping */ 

#if defined (MMU_MAP_SDRAM_OPEN_IRAM_0)

extern TT_SECTION_BLOCK tt_sdram_open_iram_at_0 [];
#undef MMU_LEVEL1_DESCRIPTORS
// Long line for readability
#define MMU_LEVEL1_DESCRIPTORS  ((TT_SECTION_BLOCK *) tt_init_sram_hivecs)
#undef MMU_MAP_BASIC

#endif

/* SDRAM at 0x0, SROMLL bit set */ 

#if defined (MMU_MAP_SDRAM_0_SROMLL)

extern TT_SECTION_BLOCK tt_sdram_at_0_w_SROMLL [];
#undef MMU_LEVEL1_DESCRIPTORS
// Long line for readability
#define MMU_LEVEL1_DESCRIPTORS  ((TT_SECTION_BLOCK *) tt_sdram_at_0_w_SROMLL)
#undef MMU_MAP_BASIC

#endif

/**********************************************************************
 * LH7A400 EVB MMU Initialization function prototypes
 *********************************************************************/

INT_32 LH7A400_init_mmu_trans_table (TRANSTABLE * tt,
                                     TT_SECTION_BLOCK * ttsbp);
INT_32 LH7A400_init_mmu_page_table (PAGETABLE * pt);
INT_32 LH7A400_init_mmu_tables_wrapper (TRANSTABLE * tt);

#endif /* LH7A400_EVBMMUINIT_H */