📄 lh7a400_evbmmuinit_data.c
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{4,0xD1800000,0xCC000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_TYPE_SECTION},
{4,0xD1C00000,0xCD000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_TYPE_SECTION},
{4,0xD2000000,0xD0000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xD2400000,0xD1000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xD2800000,0xD4000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xD2C00000,0xD5000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xD3000000,0xD8000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xD3400000,0xD9000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xD3800000,0xDC000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xD3C00000,0xDD000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
/* Flash */
{4,0x40000000,0x00000000,
L1D_AP_ALL | L1D_DOMAIN(8) | L1D_CACHEABLE |
L1D_TYPE_SECTION},
/* SRAM, dual mapped */
{2,0x00000000,0x10000000,
L1D_AP_ALL | L1D_DOMAIN(9) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{2,0x10000000,0x10000000,
L1D_AP_ALL | L1D_DOMAIN(10) |
L1D_TYPE_SECTION},
/* CPLD */
{1,0x20000000,0x20000000,
L1D_AP_ALL | L1D_DOMAIN(11) |
L1D_TYPE_SECTION},
/* Ethernet Controller on I/O board,
mapped back to its physical address */
{1,0x30000000,0x30000000,
L1D_AP_ALL | L1D_DOMAIN(12) |
L1D_TYPE_SECTION},
/* Internal RAM */
{1,0xB0000000,0xB0000000,
L1D_AP_ALL | L1D_DOMAIN(13) |
L1D_TYPE_SECTION},
/* System Registers */
{1,0x80000000,0x80000000,
L1D_AP_ALL | L1D_DOMAIN(14) |
L1D_TYPE_SECTION},
{0,0,0,0} /* Marks end of initialization array */
};
#endif
#if defined (MMU_MAP_SDRAM_OPEN_SRAM_0)
/*
* This section maps the entire SDRAM physical address space
* to the same virtual address space. This is useful for
* testing SDRAM. It dual maps external SRAM to 0x0 as cached and
* buffered, and to 0x10000000 w/o caching or buffering.
*/
TT_SECTION_BLOCK tt_sdram_open_sram_at_0 [] = {
/* 64Mbytes contiguous SDRAM */
{256,0xC0000000,0xC0000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_TYPE_SECTION},
{256,0xD0000000,0xD0000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_TYPE_SECTION},
/* Flash */
{4,0x40000000,0x00000000,
L1D_AP_ALL | L1D_DOMAIN(8) | L1D_CACHEABLE |
L1D_TYPE_SECTION},
/* SRAM, dual mapped */
{2,0x00000000,0x10000000,
L1D_AP_ALL | L1D_DOMAIN(9) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{2,0x10000000,0x10000000,
L1D_AP_ALL | L1D_DOMAIN(10) |
L1D_TYPE_SECTION},
/* CPLD */
{1,0x20000000,0x20000000,
L1D_AP_ALL | L1D_DOMAIN(11) |
L1D_TYPE_SECTION},
/* Ethernet Controller on I/O board,
mapped back to its physical address */
{1,0x30000000,0x30000000,
L1D_AP_ALL | L1D_DOMAIN(12) |
L1D_TYPE_SECTION},
/* Internal RAM */
{1,0xB0000000,0xB0000000,
L1D_AP_ALL | L1D_DOMAIN(13) |
L1D_TYPE_SECTION},
/* System Registers */
{1,0x80000000,0x80000000,
L1D_AP_ALL | L1D_DOMAIN(14) |
L1D_TYPE_SECTION},
{0,0,0,0} /* Marks end of initialization array */
};
#endif
#if defined (MMU_MAP_SDRAM_OPEN_IRAM_0)
/*
* This is an example that dual maps the internal (embedded) RAM to
* 0x0 as cached and buffered and to its physical address 0xB00000000,
* as uncached and unbuffered.
*/
TT_SECTION_BLOCK tt_sdram_open_iram_at_0 [] = {
/* 64Mbytes contiguous SDRAM */
{256,0xC0000000,0xC0000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_TYPE_SECTION},
{256,0xD0000000,0xD0000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_TYPE_SECTION},
/* Flash */
{4,0x40000000,0x00000000,
L1D_AP_ALL | L1D_DOMAIN(8) | L1D_CACHEABLE |
L1D_TYPE_SECTION},
/* SRAM */
{2,0x10000000,0x10000000,
L1D_AP_ALL | L1D_DOMAIN(9) | L1D_TYPE_SECTION},
/* CPLD */
{1,0x20000000,0x20000000,
L1D_AP_ALL | L1D_DOMAIN(11) |
L1D_TYPE_SECTION},
/* Ethernet Controller on I/O board,
mapped back to its physical address */
{1,0x30000000,0x30000000,
L1D_AP_ALL | L1D_DOMAIN(10) |
L1D_TYPE_SECTION},
/* Internal RAM, Dual Mapped */
{1,0x00000000,0xB0000000,
L1D_AP_ALL | L1D_DOMAIN(12) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{1,0xB0000000,0xB0000000,
L1D_AP_ALL | L1D_DOMAIN(13) |
L1D_TYPE_SECTION},
/* System Registers */
{1,0x80000000,0x80000000,
L1D_AP_ALL | L1D_DOMAIN(14) |
L1D_TYPE_SECTION},
{0,0,0,0} /* Marks end of initialization array */
};
#endif
#if defined (MMU_MAP_SDRAM_0_SROMLL)
/*
* This section maps the entire SDRAM physical address space
* down to 0x0. THis mapping will only work if the SROMLL bit
* is set in the SDRAM initialization. THe advantage of this
* mapping is that on the LH7A400 EVB, the entire SDRAM space can
* be accessed contiguously without "holes" in the physical address,
* which is very useful for LCD applications.
*/
TT_SECTION_BLOCK tt_sdram_at_0_w_SROMLL [] = {
/* 64Mbytes contiguous SDRAM */
{32,0x00000000,0xC0000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_TYPE_SECTION},
{32,0x02000000,0xD0000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_TYPE_SECTION},
/* Flash */
{4,0x40000000,0x00000000,
L1D_AP_ALL | L1D_DOMAIN(8) | L1D_CACHEABLE |
L1D_TYPE_SECTION},
/* SRAM, dual mapped */
{2,0x10000000,0x10000000,
L1D_AP_ALL | L1D_DOMAIN(9) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
/* CPLD */
{1,0x20000000,0x20000000,
L1D_AP_ALL | L1D_DOMAIN(11) |
L1D_TYPE_SECTION},
/* Ethernet Controller on I/O board,
mapped back to its physical address */
{1,0x30000000,0x30000000,
L1D_AP_ALL | L1D_DOMAIN(12) |
L1D_TYPE_SECTION},
/* Internal RAM */
{1,0xB0000000,0xB0000000,
L1D_AP_ALL | L1D_DOMAIN(13) |
L1D_TYPE_SECTION},
/* System Registers */
{1,0x80000000,0x80000000,
L1D_AP_ALL | L1D_DOMAIN(14) |
L1D_TYPE_SECTION},
{0,0,0,0} /* Marks end of initialization array */
};
#endif
#if defined (MMU_MAP_SDRAM_0_CACHED)
/*
* This section maps the entire SDRAM physical address space
* down to 0x0 as cached SDRAM. SDRAM is also mirrored at address
* 0xC0000000 as uncached SDRAM. This mapping will only work if
* the SROMLL bit is set in the SDRAM initialization. The advantage
* of this mapping is that code can run cached from SDRAM while
* the frame buffers can be placed in uncached SDRAM.
*/
TT_SECTION_BLOCK tt_cached_sdram_at_0 [] = {
/* 64Mbytes contiguous SDRAM, cached */
{4,0x00000000,0xC0000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x00400000,0xC1000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x00800000,0xC4000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x00C00000,0xC5000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x01000000,0xC8000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x01400000,0xC9000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x01800000,0xCC000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x01C00000,0xCD000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
/* Bank 1 of SDRAM */
{4,0x02000000,0xD0000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x02400000,0xD1000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x02800000,0xD4000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x02C00000,0xD5000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x03000000,0xD8000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x03400000,0xD9000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x03800000,0xDC000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{4,0x03C00000,0xDD000000,
L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
/* 64Mbytes contiguous SDRAM, uncached */
{4,0xC0000000,0xC0000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xC0400000,0xC1000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xC0800000,0xC4000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xC0C00000,0xC5000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xC1000000,0xC8000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xC1400000,0xC9000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xC1800000,0xCC000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
{4,0xC1C00000,0xCD000000,
L1D_AP_ALL | L1D_DOMAIN(2) | L1D_TYPE_SECTION},
/* Bank 1 of SDRAM */
{4,0xC2000000,0xD0000000,
L1D_AP_ALL | L1D_DOMAIN(3) | L1D_TYPE_SECTION},
{4,0xC2400000,0xD1000000,
L1D_AP_ALL | L1D_DOMAIN(3) | L1D_TYPE_SECTION},
{4,0xC2800000,0xD4000000,
L1D_AP_ALL | L1D_DOMAIN(3) | L1D_TYPE_SECTION},
{4,0xC2C00000,0xD5000000,
L1D_AP_ALL | L1D_DOMAIN(3) | L1D_TYPE_SECTION},
{4,0xC3000000,0xD8000000,
L1D_AP_ALL | L1D_DOMAIN(3) | L1D_TYPE_SECTION},
{4,0xC3400000,0xD9000000,
L1D_AP_ALL | L1D_DOMAIN(3) | L1D_TYPE_SECTION},
{4,0xC3800000,0xDC000000,
L1D_AP_ALL | L1D_DOMAIN(3) | L1D_TYPE_SECTION},
{4,0xC3C00000,0xDD000000,
L1D_AP_ALL | L1D_DOMAIN(3) | L1D_TYPE_SECTION},
/* Flash */
{4,0x40000000,0x00000000,
L1D_AP_ALL | L1D_DOMAIN(8) | L1D_CACHEABLE |
L1D_TYPE_SECTION},
/* SRAM, dual mapped */
{2,0x10000000,0x10000000,
L1D_AP_ALL | L1D_DOMAIN(9) | L1D_CACHEABLE |
L1D_TYPE_SECTION},
/* CPLD */
{1,0x20000000,0x20000000,
L1D_AP_ALL | L1D_DOMAIN(11) |
L1D_TYPE_SECTION},
/* Ethernet Controller on I/O board,
mapped back to its physical address */
{1,0x30000000,0x30000000,
L1D_AP_ALL | L1D_DOMAIN(12) |
L1D_TYPE_SECTION},
/* Internal RAM */
{1,0xB0000000,0xB0000000,
L1D_AP_ALL | L1D_DOMAIN(13) |
L1D_TYPE_SECTION},
/* System Registers */
{1,0x80000000,0x80000000,
L1D_AP_ALL | L1D_DOMAIN(14) |
L1D_TYPE_SECTION},
/* CompactFlash section 1 */
{1,0x60000000,0x60000000,
L1D_AP_ALL | L1D_DOMAIN(14) |
L1D_TYPE_SECTION},
/* CompactFlash section 2 */
{1,0x70000000,0x70000000,
L1D_AP_ALL | L1D_DOMAIN(14) |
L1D_TYPE_SECTION},
{0,0,0,0} /* Marks end of initialization array */
};
#endif
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