lh7a400_evbmmuinit_data.c

sharp的arm920t 7A400的评估板附带光盘Sharp KEVLH7A400 v0.3b Welcome to the SHARP KEV7A400 Evaluation board

/***********************************************************************
 * $Workfile:   LH7A400_evbmmuinit_data.c  $
 * $Revision:   1.0  $
 * $Author:   WellsK  $
 * $Date:   Sep 23 2002 13:52:02  $
 *
 * Project: LH7A400 Evaluation Board
 *
 * Description:
 *		This file contains the following information for the
 *		LH7A400 Evaluation Board:
 *
 *		    Variants of initialization data for the Translation Table
 *		    and Page Tables.
 *
 *		Several alternative mappings of the Translation Tables are
 *		provided.
 *
 * References:
 *      (1) Sharp LH7A400 Universal Microcontroller User's Guide,
 *      Version x.x, Sharp Microelectronics of the Americas, Inc.
 *
 * Revision History:
 * $Log:   //smaicnt2/pvcs/VM/CDROM/archives/KEV7A400/Software/Startup_lite/LH7A400_evbmmuinit_data.c-arc  $
 * 
 *    Rev 1.0   Sep 23 2002 13:52:02   WellsK
 * Initial revision.
 * 
 *    Rev 1.0   Sep 14 2002 11:38:06   WellsK
 * Initial revision.
 * 
 *    Rev 1.1   Jun 13 2002 14:26:06   BarnettH
 * Changed tt_init_basic, including mapping Asynch Flash to 0x90000000, adding PCMCIA and Compact Flash, multiply mapping SDRAM.
 * 
 *    Rev 1.0   Jun 05 2002 11:02:48   BarnettH
 * Initial revision.
 * 
 ***********************************************************************
 * 
 *  Copyright (c) 2002 Sharp Microelectronics of the Americas
 *
 *  All rights reserved
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 *  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 *  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
 *  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 *  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
 *  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
 *  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT.  USE OF THIS SOURCE
 *  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 **********************************************************************/

#include "LH7A400_evb.h"
#include "LH7A400_evbmmuinit.h"

/**********************************************************************
 * LH7A400 EVB MMU Initialization
 *
 * Basic Translation Table Initialization Configuration
 *
 * Contains Level 1 descriptors of contiguous blocks of the
 * Translation Table.
 *
 * This is a user-provided array of variable size.  Each entry defines a
 * block of virtual memory which maps to contiguous physical memory.
 * It is only necessary to map blocks of actual memory and register banks.
 * All other entries will be mapped to type FAULT by the
 * initialization function.
 *
 * This defines storage.
 *********************************************************************/

#if defined (MMU_MAP_BASIC)
/***********************************************************************    
 * Basic Memory Map for startup.
 **********************************************************************/
TT_SECTION_BLOCK tt_init_basic [] = {
    /* 64Mbytes of SDRAM mapped as a contiguous block.
     *  This is based on Micron MT48LC328M16A2 chips
     *  with SROMLL bit set low. */

    /* 32 MB Bank 0 of SDRAM, contiguous, cacheable, bufferable */
    {4, 0x00000000, 0xC0000000, 
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x00400000, 0xC1000000, 
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x00800000, 0xC4000000, 
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x00C00000, 0xC5000000, 
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x01000000, 0xC8000000, 
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x01400000, 0xC9000000, 
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x01800000, 0xCC000000, 
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x01C00000, 0xCD000000, 
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 

    /* 32 MB Bank 1 of SDRAM, contiguous, cacheable, bufferable */
    {4, 0x02000000, 0xD0000000, 
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x02400000, 0xD1000000, 
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x02800000, 0xD4000000, 
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x02C00000, 0xD5000000, 
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x03000000, 0xD8000000, 
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x03400000, 0xD9000000, 
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x03800000, 0xDC000000, 
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 
    {4, 0x03C00000, 0xDD000000, 
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION}, 

    /* 64MB of non-cached non-buffered SDRAM mapped as a contiguous
     * block, based at physical address of Bank 0. */ 
    /* 32MB Bank 0 non-cached, non, buffered contiguous block */
    {4, 0xC0000000, 0xC0000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC0400000, 0xC1000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC0800000, 0xC4000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC0C00000, 0xC5000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC1000000, 0xC8000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC1400000, 0xC9000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC1800000, 0xCC000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC1C00000, 0xCD000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    /* 32MB Bank 0 non-cached, non, buffered contiguous block */
    {4, 0xC2000000, 0xD0000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC2400000, 0xD1000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC2800000, 0xD4000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC2C00000, 0xD5000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC3000000, 0xD8000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC3400000, 0xD9000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC3800000, 0xDC000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 
    {4, 0xC3C00000, 0xDD000000, 
        L1D_AP_ALL | L1D_DOMAIN(2) |
            L1D_TYPE_SECTION}, 

    /* Flash */
    {8, 0x90000000, 0x00000000, 
        L1D_AP_ALL | L1D_DOMAIN(8) | L1D_CACHEABLE |
            L1D_TYPE_SECTION}, 

    /* Synchronous Flash, mapped to physical address */
    {8, 0xF0000000, 0xF0000000, 
        L1D_AP_ALL | L1D_DOMAIN(8) | L1D_CACHEABLE |
            L1D_TYPE_SECTION}, 

    /* SRAM, mapped to physical address */
    {2, 0x10000000, 0x10000000, 
      L1D_AP_ALL | L1D_DOMAIN(9) |
            L1D_TYPE_SECTION}, 

    /* CPLD, mapped to physical address */
    {1, 0x20000000, 0x20000000, 
        L1D_AP_ALL | L1D_DOMAIN(11) |
            L1D_TYPE_SECTION}, 

    /* Ethernet Controller on I/O board, mapped to physical address */
    {1, 0x30000000, 0x30000000, 
        L1D_AP_ALL | L1D_DOMAIN(12) |
            L1D_TYPE_SECTION}, 

    /* Internal RAM, mapped to physical address */
    {1, 0xB0000000, 0xB0000000, 
        L1D_AP_ALL | L1D_DOMAIN(13) |
            L1D_TYPE_SECTION}, 

    /* System Registers, mapped to physical address */
    {1, 0x80000000, 0x80000000, 
        L1D_AP_ALL | L1D_DOMAIN(14) |
            L1D_TYPE_SECTION}, 

    /* PCMCIA 1, mapped to physical address */
    {128,0x40000000,0x40000000,
        L1D_AP_ALL | L1D_DOMAIN(14) |
            L1D_TYPE_SECTION},
    /* PCMCIA 2, mapped to physical address */
    {128,0x50000000,0x50000000,
        L1D_AP_ALL | L1D_DOMAIN(14) |
            L1D_TYPE_SECTION},

    /* CompactFlash 1, mapped to physical address */
    {1,0x60000000,0x60000000,
        L1D_AP_ALL | L1D_DOMAIN(14) |
            L1D_TYPE_SECTION},
    /* CompactFlash 2, mapped to physical address */
    {1,0x70000000,0x70000000,
        L1D_AP_ALL | L1D_DOMAIN(14) |
            L1D_TYPE_SECTION},

    {0, 0, 0, 0}  /* Marks end of initialization array.  Required! */
};
#endif

#if defined (MMU_MAP_SRAM_0)
/*
 * This alternate EVB mapping puts:
 * SRAM at 0x0, Cacheable and Bufferable
 * The same SRAM at 0x10000000, not Cacheable and not Bufferable
 * SDRAM bank 0 at 0xC0000000, (see code for C/B state)
 * SDRAM bank 1 at 0xC2000000, (see code for C/B state)
 * Alternately, SDRAM bank 0 & 1 mapped to 0xD0000000 non-cached &
 * non-buffered.
 *
 * Flash, CPLD, Ethernet Controller, Internal RAM, and Registers 
 * are all mapped so that their Virtual Addresses are the same as 
 * their Physical Addresses.
 * Flash is mapped as Cacheable but not bufferable.  CPLD, Internal
 * RAM, Ethernet Controlller and Registers are all mapped as not 
 * Cacheable, and not Bufferable.
 */
TT_SECTION_BLOCK tt_init_sram_at_0 [] = {
    /* 64Mbytes contiguous SDRAM */
    {4,0xC0000000,0xC0000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC0400000,0xC1000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC0800000,0xC4000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC0C00000,0xC5000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC1000000,0xC8000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC1400000,0xC9000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC1800000,0xCC000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC1C00000,0xCD000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC2000000,0xD0000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC2400000,0xD1000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC2800000,0xD4000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC2C00000,0xD5000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC3000000,0xD8000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC3400000,0xD9000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC3800000,0xDC000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    {4,0xC3C00000,0xDD000000,
        L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
            L1D_TYPE_SECTION},
    /* 64Mbytes contiguous non-cached/non-buffered SDRAM */
    {4,0xD0000000,0xC0000000,
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_TYPE_SECTION},
    {4,0xD0400000,0xC1000000,
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_TYPE_SECTION},
    {4,0xD0800000,0xC4000000,
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_TYPE_SECTION},
    {4,0xD0C00000,0xC5000000,
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_TYPE_SECTION},
    {4,0xD1000000,0xC8000000,
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_TYPE_SECTION},
    {4,0xD1400000,0xC9000000,
        L1D_AP_ALL | L1D_DOMAIN(1) | L1D_TYPE_SECTION},