lh7a400_crt0.s

sharp的arm920t 7A400的评估板附带光盘Sharp KEVLH7A400 v0.3b Welcome to the SHARP KEV7A400 Evaluation board

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;  $Workfile:   LH7A400_crt0.s  $
;  $Revision:   1.0  $
;  $Author:   WellsK  $
;  $Date:   Sep 23 2002 13:52:02  $
; 
;  Project: LH7A400 RAM Initialization
; 
;  Description:
;       C Runtime Initialization
;
;   This file is used to put the LH7A400 processor modes in a 'sane'
;   state so the Library initialization functions automatically linked
;   in by an invocation of "main ()" do not break while doing THEIR
;   initialization.  The Entry point should be identified as being in
;   this code.  It will jump to __main() after running.
;
;   This file is used only for code which runs out of RAM and which
;   invokes the function "main()".  It is NOT needed for the Flash
;   based Startup image; startup provides its own mode initialization.
; 
;  Revision History:
;
;  $Log:   //smaicnt2/pvcs/VM/CDROM/archives/KEV7A400/Software/Startup_lite/LH7A400_crt0.s-arc  $
; 
;    Rev 1.0   Sep 23 2002 13:52:02   WellsK
; Initial revision.
; 
;    Rev 1.0   Sep 14 2002 11:38:06   WellsK
; Initial revision.
; 
;    Rev 1.2   Aug 28 2002 14:37:32   BarnettH
; Moved the file to "startup" area, and changed comments to 
; clarify its usage.
; 
;    Rev 1.1   Jul 26 2002 17:56:02   BarnettH
; Interim work towards Milestone 3
; 
;    Rev 1.0   Jul 10 2002 14:31:52   BarnettH
; Initial revision.
;  
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;  
;   Copyright (c) 2002 Sharp Microelectronics of the Americas
; 
;   All rights reserved
; 
;   SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
;   OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
;   AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES,
;   SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
; 
;   SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY
;   FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A
;   SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT.  USE OF THIS SOURCE
;   FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
; 
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	AREA 	crt0, CODE 	; name this block of code

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; Board Definitions, MMU and Coprocessor definitions, Clock definitions
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	INCLUDE	lh7A400_evb.i

; Keep total stack size within 128K
CRT0_SVC_STACK_SIZE		EQU		(32 * 1024)	; running stack for svc
CRT0_IRQ_STACK_SIZE		EQU		(32 * 1024)	; running stack for irq
CRT0_UNDEF_STACK_SIZE	EQU		(8 * 1024)	; may be used by debugger
CRT0_FIQ_STACK_SIZE		EQU		(4 * 1024)	; running stack for fiq
CRT0_ABORT_STACK_SIZE	EQU		(4 * 1024)	; running stack for abt
CRT0_SYSTEM_STACK_SIZE	EQU		(32 * 1024); running stack for usr/sys.

; MMU_MODE_STACK_BASE is defined in LH7A400_evb.i
CRT0_SVC_STACK_BASE		EQU	MMU_MODE_STACK_BASE
CRT0_IRQ_STACK_BASE		EQU	(CRT0_SVC_STACK_BASE - CRT0_SVC_STACK_SIZE)
CRT0_UNDEF_STACK_BASE	EQU	(CRT0_IRQ_STACK_BASE - CRT0_IRQ_STACK_SIZE)
CRT0_FIQ_STACK_BASE		EQU	(CRT0_UNDEF_STACK_BASE - CRT0_UNDEF_STACK_SIZE)
CRT0_ABORT_STACK_BASE	EQU	(CRT0_FIQ_STACK_BASE - CRT0_FIQ_STACK_SIZE)
CRT0_SYSTEM_STACK_BASE	EQU	(CRT0_ABORT_STACK_BASE - CRT0_ABORT_STACK_SIZE)
CRT0_END_STACK_BASE		EQU	(CRT0_SYSTEM_STACK_BASE - CRT0_SYSTEM_STACK_SIZE)

; init mode stacks in low memory 
ENTRY
	EXPORT ENTRY
crt0_entry
	EXPORT crt0_entry
crt0_clear_caches
    ; Flush the TLB and Caches
    MVN     r1,#0
    ; Flush the TLB
    MCR     MMU_CP, 0, r1, MMU_REG_TLB_OP, c7, 0
    ; Invalidate both I and D Cache
    MCR     MMU_CP, 0, r1, MMU_REG_CACHE_OP, c7, 0
    NOP
    NOP
    NOP
crt0_mode_init_stacks
;	All interrupts disabled at core
	MOV     r1,#I_MASK:OR:F_MASK ; No Interrupts
; Enter IRQ mode and setup the IRQ stack pointer
	ORR     r0,r1,#MODE_IRQ
   	MSR     cpsr_cxsf, r0
   	LDR     r13, =CRT0_IRQ_STACK_BASE
    
; Enter FIQ mode and setup the FIQ stack pointer
	ORR     r0,r1,#MODE_FIQ
    MSR     cpsr_cxsf, r0
    LDR     r13, =CRT0_FIQ_STACK_BASE
    
; Enter Abort mode and setup the Abort stack pointer
	ORR     r0,r1,#MODE_ABORT
    MSR     cpsr_cxsf, r0
    LDR     r13, =CRT0_ABORT_STACK_BASE
    
; Enter Undefined mode and setup the Undefined stack pointer
	ORR     r0,r1,#MODE_UNDEF
    MSR     cpsr_cxsf, r0
    LDR     r13, =CRT0_UNDEF_STACK_BASE
    
; Enter System mode and setup the User/System stack pointer
	ORR     r0,r1,#MODE_SYSTEM
    MSR     cpsr_cxsf, r0
    LDR     r13, =CRT0_SYSTEM_STACK_BASE

; Enter SVC mode and setup the SVC stack pointer.
; This is the mode for E_Entry.

	ORR     r0,r1,#MODE_SVC
    MSR     cpsr_cxsf, r0
    LDR     r13, =CRT0_SVC_STACK_BASE

;disable all interrupts at interrupt controller
disable_interrupts
	MVN		r0,#0
	LDR		r2,=INTC_REG_BASE
	STR		r0,[r2,#INTC_INTENC_OFFSET]

; Enter SVC Mode, Interrupts disabled
	ORR     r0,r1,#MODE_SVC 
    MSR     cpsr_cxsf, r0

; Jump to library initialization code at __main ()
	IMPORT	__main
    B       __main

crt0_Limit
    END