evb_aruba.abl

sharp的arm920t 7A400的评估板附带光盘Sharp KEVLH7A400 v0.3b Welcome to the SHARP KEV7A400 Evaluation board

 //   TEST_OUT = TEST_IN; "Preserve unused pins
  
  // address decodes for all functions
    CPLD_CS         = nCS2;  "Access peripherals in or controlled by CPLD
    OPT_CS          = CPLD_CS & (Addr == ^h0); "Read only option DIP switch register (8-bits wide)
    KEYS_CS         = CPLD_CS & (Addr == ^h1); "read push Buttons connected to CPLD (8-bits wide), write reset latch
    INT_STAT_CS     = CPLD_CS & (Addr == ^h2); "read Interrupt events status register (8-bits wide), write reset latch
    BOOT_MMC_CS     = CPLD_CS & (Addr == ^h3); "read only BOOT device & MMC status register (8-bits wide)
    MATRIX_CS       = CPLD_CS & (Addr == ^h4); "Read only matrix keypad (16 bits wide)
    DISP_CS         = CPLD_CS & (Addr == ^h5); "read only Display board switches (8-bits wide)

    LCDPWR_CS       = CPLD_CS & (Addr == ^h6); "read/Write LCD control register (8-bits wide)

    IO_REG_CS       = CPLD_CS & (Addr == ^h0); "write only I/O board latch strobe (8-bits wide)
    PB_MASK_CS      = CPLD_CS & (Addr == ^h4); "write only Switch interrupt mask register (8 bits wide)
    INT_MASK_CS     = CPLD_CS & (Addr == ^h5); "write only External Interrupt event mask register (8-bits wide)
    LED_CS          = CPLD_CS & (Addr == ^h7); "write only LED register (16 bits wide)
    
// Buffered data bus control
    nDB_OE = nCS0 # nCS1 # nCS2 # nCS3 # nPC1_EN # nPC2_EN # CS6 # CS7; "driven active for both reads & writes
// nDB_DIR  = nMOE # PC_DIR; "pin is low for read, high for write

//  Changed the equation for nDB_DIR to allow correct access to the PC Card
//  (mcm: Set to true to indicate a read if nMOE says it's a read or PC_DIR says it's a read or both PC slots
//     are enabled; conversely, set to false to indicate a write only if nMOE says it's not a read, PC_DIR says it's
//     not a read, and there aren't two slots enabled)
    nDB_DIR         = (nMOE # ((!PC_DIR) & (nPC1_EN # nPC2_EN))) # 
                      (nPC1_EN & nPC2_EN);

// Memory mapped clocks & strobes	 
    nIO_REG_CLK     = IO_REG_CS & nMWE0;
    nLED_CLK        = LED_CS & nMWE0;
    nMATRIX_RD      = MATRIX_CS & nMOE;
    nDISP_RD        = DISP_CS & nMOE;

    RESET_KEYS      = Write_Strobe & KEYS_CS; "strobe to reset latched key status bits
    RESET_INT_STAT  = Write_Strobe & INT_STAT_CS; "strobe to reset latched key status bits
    Write_Data      = BD.pin; "interal write bus = BD bus

// Invert signals
    nCS6            = CS6;
    nCS7            = CS7;

// LCD Power Control
    POWCTL          := Write_Data[4..0];
    !POWCTL.clk     = LCDPWR_CS & Write_Strobe; "clk at end of WR cycle
    POWCTL.aclr     = nMAIN_RST;

    // latched Interrupt Event reset Control
    // leading edge of interrupt sets bit in reg. high
    // bit is cleared by main reset or writing 1 to corresponding register bit
//    L_nSW           := 1;
//    L_nSW.clk       = Int_PB;
//    L_nSW.aclr      = (RESET_INT_STAT & Write_Data5) # nMAIN_RST # !nSW_MASK;

//    LnINT_clr       = (RESET_INT_STAT & Write_Data4);
    L_nINT          := 1;
    !L_nINT.clk     = nINT; "clk on leading edge of switch depressed
//    L_nINT.aclr     = LnINT_clr # nMAIN_RST # !nINT_MASK;
    L_nINT.aclr     = (RESET_INT_STAT & Write_Data4) # nMAIN_RST # !nINT_MASK;

    L_ETH           := 1;
    L_ETH.clk       = INT_ETH; "clk on leading edge of switch depressed
    L_ETH.aclr      = (RESET_INT_STAT & Write_Data3) # nMAIN_RST # !ETH_MASK;
 
    L_CF            := 1;
    L_CF.clk        = INT_CF_IDE; "clk on leading edge of switch depressed
    L_CF.aclr       = (RESET_INT_STAT & Write_Data2) # nMAIN_RST # !CF_MASK;

    L_RI            := 1;
    !L_RI.clk       = nRI2; "clk on leading edge of switch depressed
    L_RI.aclr       = (RESET_INT_STAT & Write_Data1) # nMAIN_RST # !RI_MASK;
 
    L_MMC           := 1;
    !L_MMC.clk      = nMMC_CD; "clk on leading edge of switch depressed
    L_MMC.aclr      = (RESET_INT_STAT & Write_Data0) # nMAIN_RST # !MMC_CD_MASK;

// External Switches Internal reset Control
//    I_Keys := 1;
//    !I_Keys.clk     = Keys; "clk on leading edge of switch depressed
//    I_Keys.aclr     = (RESET_KEYS & Write_Data) # nMAIN_RST;

// internal strobes for all functions
    Read_Enable     = nMOE;
    Write_Strobe    = nMWE0;

  // external data bus, qualify with only internal CPLD register locations djc 
    BD[7..0].oe     = Read_Enable & CPLD_CS & (OPT_CS # KEYS_CS # 
                      INT_STAT_CS # BOOT_MMC_CS # LCDPWR_CS); 
    BD              = Read_Data;

// !nCPLD_IRQ interrupt
// !nCPLD_IRQ mask bit definitions
//    nSW_MASK        = INTMASK5.q;
    nINT_MASK       = INTMASK4.q;
    ETH_MASK        = INTMASK3.q;
    CF_MASK         = INTMASK2.q;
    RI_MASK         = INTMASK1.q;
    MMC_CD_MASK     = INTMASK0.q;

    nSW8_MASK       = PB_MASK7.q;
    nSW7_MASK       = PB_MASK6.q;
    nSW6_MASK       = PB_MASK5.q;
    nSW5_MASK       = PB_MASK4.q;
    nSW4_MASK       = PB_MASK3.q;
    nSW3_MASK       = PB_MASK2.q;
    nSW2_MASK       = PB_MASK1.q;
    nSW1_MASK       = PB_MASK0.q;

//    INTMASK_U       := Write_Data[5..0];
    INTMASK_U       := Write_Data[4..0];
    !INTMASK_U.clk  = INT_MASK_CS & Write_Strobe; "clk at end of WR cycle
    INTMASK_U.aclr  = nMAIN_RST;

    INTMASK_L       := Write_Data[7..0];
    !INTMASK_L.clk  = PB_MASK_CS & Write_Strobe; "clk at end of WR cycle
    INTMASK_L.aclr  = nMAIN_RST;
    
//    QnSW            = L_nSW.q & nSW_MASK;
    QnINT           = L_nINT.q & nINT_MASK;
    QETH            = L_ETH.q & ETH_MASK;
    QCF             = L_CF.q & CF_MASK;
    QRI             = L_RI.q & RI_MASK;
    QMMC            = L_MMC.q & MMC_CD_MASK;

    QSW8            = nSW8 & nSW8_MASK;
    QSW7            = nSW7 & nSW7_MASK;
    QSW6            = nSW6 & nSW6_MASK;
    QSW5            = nSW5 & nSW5_MASK;
    QSW4            = nSW4 & nSW4_MASK;
    QSW3            = nSW3 & nSW3_MASK;
    QSW2            = nSW2 & nSW2_MASK;
    QSW1            = nSW1 & nSW1_MASK;

    IntAny          = QnINT # QETH # QCF # QRI # QMMC;
//    IntAny          = QnINT # QETH # QCF # QRI # QMMC # QnSW;
    Int_PB          = QSW8 # QSW7 # QSW6 # QSW5 # QSW4 # QSW3 # QSW2 # QSW1;

    nCPLD_IRQ.oe    = IntAny # Int_PB;
    nCPLD_IRQ       = 1;  "simulated open-drain output

  // internal read bus
    when (Read_Enable)
    then
    {
        when (OPT_CS)
        then
            Read_Data = Option_SW;
        else when (KEYS_CS)
        then
        {
            Read_Data = Keys; "Qualify with keys interrupt mask register
        }
        else when ( INT_STAT_CS )
        then
        {
//            Read_Data[7..6] = 0; "Qualify with event interrupt mask register
            Read_Data[7..5] = 0; "Qualify with event interrupt mask register
//            Read_Data5 = L_nSW.q;
            Read_Data4 = L_nINT.q;
            Read_Data3 = L_ETH.q;
            Read_Data2 = L_CF.q;
            Read_Data1 = L_RI.q;
            Read_Data0 = L_MMC.q;
        }
        else when ( BOOT_MMC_CS )
        then
        {
            Read_Data[7] = 0;
            Read_Data[6] = nSRAM_BOOT;
            Read_Data[5] = nSYNC_BOOT;
            Read_Data[4] = nFLASH_BOOT;
            Read_Data[3] = 0;
            Read_Data[2] = 0;
            Read_Data[1] = MMC_WP;
            Read_Data[0] = nMMC_CD;
        }
        else when ( LCDPWR_CS )
        then
        {
            Read_Data[7..5] = 0;
            Read_Data4 = LCD_PWR_EN.q;
            Read_Data3 = LCD_OE.q;
            Read_Data2 = DISP_EN.q;
            Read_Data1 = BKLT_ON.q;
            Read_Data0 = nSHUT_V.q;
        }
        else
            Read_Data = .X.;
    }
    else
        Read_Data = .X.;

end Evb_A400