evb_aruba.abl

sharp的arm920t 7A400的评估板附带光盘Sharp KEVLH7A400 v0.3b Welcome to the SHARP KEV7A400 Evaluation board

////////////////////////////////////////////////////////////////////////
// $Workfile:   evb_Aruba.abl  $
// $Revision:   1.9  $
// $Author:   MaysR  $
// $Date:   Jun 24 2002 18:55:38  $
//
// Project: LH7A400 EVB
//
// Description:
//   This file contains the CPLD code for the XCR3064XL CPLD on the
//   Sharp LH7A400 evaluation board
//
// Revision History:
// $Log:   //smaicnt2/pvcs/VM/CHIPS/archives/LH7A400/CPLD/evb_Aruba.abl-arc  $
//
//   Rev 1.9   Jun 24 2002 18:55:38   MaysR
//Updated files for new configuration settings.
//
//   Rev 1.8   May 22 2002 20:18:44   maysr
//Changed sense of option switches, and inverted them.  Saves 80 bytes of startup code.
//
//   Rev 1.7   09 Apr 2002 16:47:14   kovitzp
//Removed TEST_OUT pin. Pin 47 is now LCD_PWR_EN.
//LCD_PWR_EN  pin value is stored in bit 4 of the LCD Power 
//Control Register. TEST_IN (pin 88) will be optimized away.
//
//   Rev 1.6   Feb 13 2002 00:41:08   MillerM
//Turns out that PVCS log entries longer than 255 characters
//break the ABEL compiler. Changed the nDB_DIR equation
//to make the error cases clearer.
//
//   Rev 1.5   Feb 12 2002 20:32:24   MillerM
//Changed equation for nDB_DIR again. Since it's declared with negative logic
//(1 equates to a read), and PC_DIR is positive logic (1 equates to a write),
//we must invert PC_DIR in the equation. The or term for the nPCx_EN signals
//was changed to an exclusive or to make sure that in the erroneous case where
//both PCx_EN signals are asserted, no write takes place.
//
//   Rev 1.4   Feb 12 2002 17:25:04   MillerM
//Changed equation for nDB_DIR. Was
//nDB_DIR = nMOE # (PC_DIR $ (nPC1_EN # nPC2_EN)), is
//nDB_DIR = nMOE # (PC_DIR & (nPC1_EN # nPC2_EN)).
//
//   Rev 1.3   Feb 12 2002 15:16:04   StokerD
//Expanded Keywords
//
//
// COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
// CAMAS, WA
////////////////////////////////////////////////////////////////////////
"        1         2         3         4         5         6         7
"23456789012345678901234567890123456789012345678901234567890123456789012345

module Evb_A400

title 'Peripheral and glue logic for LH7A400 Evaluation Board'
// LH7A400 CPLD is derived from 520 eval board CPLD.
// CPLD Code Version A400_00_2
// _0 Latch external interrupt events and external switches
// _1 delete external switch latches
// _2 qualify External Latched Interrupt Event status Register with mask register
// I tried to qualify pushbutton status register with pushbutton Interrupt mask register
// but that would not fit into the design with the current -01 EVB pinout.
declarations
  // low_true inputs
    !nMAIN_RST      pin 23;  "System reset (nPOR # nPWRFL # nURESET cpu pins)
    !nCS3..!nCS0    pin 81, 83, 84, 85;  "CPU nCSx pin
    !nMOE           pin 76;  "CPU nMOE pin
    !nPC1_EN        pin 69;  "CPU PCMCIA ENA1 pin
    !nPC2_EN        pin 68;  "CPU PCMCIA ENA2 pin
    !nSW8..!nSW1    pin 97, 96, 94, 93, 92, 63, 64, 65;  "User buttons pin
    !OPT1..!OPT8    pin 14, 13, 12, 10, 9, 8, 6, 100;  "CPU brd option switches
    !nINT           pin 98;  "Interrupt button pin
    !nMWE0          pin 90;  "CPU nMWE0 pin
    !nFLASH_BOOT    pin 44;  "nFLASH_BOOT status bit
    !nSYNC_BOOT     pin 42;  "nSYNC_BOOT status bit
    !nSRAM_BOOT     pin 41;  "nSRAM_BOOT status bit
    !nRI2           pin 25;  "RING INDICATOR interrupt status bit
    !nMMC_CD        pin 16;  "MMC card detect status bit
     
  // high-true inputs
    CS7..CS6        pin 79, 80;  "CPU CSx pin
    PC_DIR          pin 67;  "CPU PCMCIA direction pin
    BA3..BA1        pin 89, 45, 46;  "address bus
    INT_ETH         pin 29;  "Ethernet Interrupt status bit
    INT_CF_IDE      pin 30;  "Compact Flash Interrupt status bit
    MMC_WP          pin 40;  "MMC write protect status bit
//    TEST_IN         pin 88; "Test input pin

  // low-true outputs
    !nCS7..!nCS6    pin 71, 75 istype 'com';  "low active CSx
    !nIO_REG_CLK    pin 17 istype 'com';  "I/O board write strobe
    !nLED_CLK       pin 19 istype 'com';  "LED register write enables
    !nMATRIX_RD     pin 20 istype 'com';  "matrix switches read enable
    !nDISP_RD       pin 21 istype 'com';  "Display options read enable
    !nDB_OE         pin 31 istype 'com';  "Data Bus Buffer Output Enable
    !nDB_DIR        pin 32 istype 'com';  "Data Bus Buffer direction
    !nCPLD_IRQ      pin 99 istype 'com';  "CPU PF1 pin (tri-state)
    !nSHUT_V        pin 35 istype 'reg, buffer';  "Shut down 26.8V

  // high_true outputs
    BD7..BD0        pin 61, 60, 58, 57, 56, 54, 52, 48 istype 'com';  "CPU data bus (BD7..BD0)
    LCD_OE          pin 36 istype 'reg, buffer';  "LCD Output Enable
    DISP_EN         pin 37 istype 'reg, buffer';  "Display Enable
    BKLT_ON         pin 33 istype 'reg, buffer';  "Back light on
    LCD_PWR_EN      pin 47 istype 'reg, buffer'; " power pin output pin
// TEST_OUT pin 47 istype 'com'; " Test output pin
    
  // buried nodes (most of these will be optimized away)
    CPLD_CS         node istype 'com';  "Access peripherals in or controlled by CPLD
    OPT_CS          node istype 'com'; "Read option DIP switch register (8-bits wide)
    KEYS_CS         node istype 'com'; "push Buttons connected to CPLD
    INT_STAT_CS     node istype 'com'; "Interrupt events status register
    BOOT_MMC_CS     node istype 'com'; "BOOT device & MMC status register
    MATRIX_CS       node istype 'com'; "Read matrix keypad
    DISP_CS         node istype 'com'; "Display board switches
    LED_CS          node istype 'com'; "write-only LED register (16 bits wide)
    IO_REG_CS       node istype 'com'; "I/O board latch strobe
    LCDPWR_CS       node istype 'com'; "LCD Power control register strobe
    PB_MASK_CS      node istype 'com'; "Switch Intr mask register latch strobe
    INT_MASK_CS     node istype 'com'; "combined Intr mask register latch strobe
    Write_Strobe    node istype 'com'; "I/O write strobe
    Read_Enable     node istype 'com'; "I/O read strobe
    RESET_KEYS      node istype 'com'; "reset keys latch strobe
    RESET_INT_STAT  node istype 'com'; "reset interrupt latch strobe
//  I_Keys8..I_Keys1    node istype 'reg, buffer'; "Keys latch
    Read_Data7..Read_Data0      node istype 'com'; "internal read data bus
    Write_Data7..Write_Data0    node istype 'com'; "internal write data bus
    INTMASK4..INTMASK0          node istype 'reg, buffer'; "Interrupt mask register
//    INTMASK5..INTMASK0          node istype 'reg, buffer'; "Interrupt mask register
    PB_MASK7..PB_MASK0          node istype 'reg, buffer'; "Interrupt mask register
    Int_PB          node istype 'com'; "Any interrupt condition
    IntAny          node istype 'com'; "Any interrupt condition
//    L_nSW           node istype 'reg, buffer'; "latched nINT switch interrupt
    L_nINT          node istype 'reg, buffer'; "latched nINT switch interrupt
    L_ETH           node istype 'reg, buffer'; "latched INT_ETH interrupt
    L_CF            node istype 'reg, buffer'; "latched INT_CF_IDE interrupt
    L_RI            node istype 'reg, buffer'; "latched nRI2 interrupt 
    L_MMC           node istype 'reg, buffer'; "latched nMMC_CD interrupt
//    LnINT_clr       node istype 'com'; "reset nINT latch
//    nSW_MASK        node istype 'com'; "intrrupt mask bit
    nINT_MASK       node istype 'com'; "intrrupt mask bit
    ETH_MASK        node istype 'com'; "intrrupt mask bit
    CF_MASK         node istype 'com'; "intrrupt mask bit
    RI_MASK         node istype 'com'; "intrrupt mask bit
    MMC_CD_MASK     node istype 'com'; "intrrupt mask bit
    nSW8_MASK       node istype 'com'; "intrrupt mask bit
    nSW7_MASK       node istype 'com'; "intrrupt mask bit
    nSW6_MASK       node istype 'com'; "intrrupt mask bit
    nSW5_MASK       node istype 'com'; "intrrupt mask bit
    nSW4_MASK       node istype 'com'; "intrrupt mask bit
    nSW3_MASK       node istype 'com'; "intrrupt mask bit
    nSW2_MASK       node istype 'com'; "intrrupt mask bit
    nSW1_MASK       node istype 'com'; "intrrupt mask bit
//    QnSW            node istype 'com'; "Qualified bit
    QnINT           node istype 'com'; "Qualified bit
    QETH            node istype 'com'; "Qualified bit
    QCF             node istype 'com'; "Qualified bit
    QRI             node istype 'com'; "Qualified bit
    QMMC            node istype 'com'; "Qualified bit
    QSW8            node istype 'com'; "Qualified bit
    QSW7            node istype 'com'; "Qualified bit
    QSW6            node istype 'com'; "Qualified bit
    QSW5            node istype 'com'; "Qualified bit
    QSW4            node istype 'com'; "Qualified bit
    QSW3            node istype 'com'; "Qualified bit
    QSW2            node istype 'com'; "Qualified bit
    QSW1            node istype 'com'; "Qualified bit

  // macros
    Addr        = [BA3..BA1];
    BD          = [BD7..BD0];
    Option_SW   = [OPT8..OPT1];
    Read_Data   = [Read_Data7..Read_Data0];
    Write_Data  = [Write_Data7..Write_Data0];
    Keys        = [nSW8..nSW1];
//   I_Keys      = [I_Keys8..I_Keys1];
    POWCTL      = [LCD_PWR_EN, LCD_OE, DISP_EN, BKLT_ON, nSHUT_V];
    INTMASK_U   = [INTMASK4..INTMASK0];
//    INTMASK_U   = [INTMASK5..INTMASK0];
    INTMASK_L   = [PB_MASK7..PB_MASK0];
//    KEYS_MASK   = [nSW8_MASK, nSW7_MASK, nSW6_MASK, nSW5_MASK, 
//                   nSW4_MASK, nSW3_MASK, nSW2_MASK, nSW1_MASK];

    // constants

equations

"sometimes needed to keep ABEL optimizer from crashing
"(see Xilinx app note XAPP109 p. 7)
  @carry 2;

  // test pins -- currently not used
    "test out pins are for probing internal nodes
    "test in pin is connected to a control jumper
    "set Test_Out=Test_In to prevent them from being optimized away