_info

VHDL traffic light control

m255
13
cModel Technology
dD:\Modeltech_6.1f\examples
Edecoder
w1143714834
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/HDL/Decoder.vhd
l0
L4
V4WkihchEoi9ZE_::GGOSA0
OE;C;6.1f;31
32
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Adecoder1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work decoder 4WkihchEoi9ZE_::GGOSA0
l28
L12
VH9a^OaE[T=k6e[:2;5:mF0
OE;C;6.1f;31
32
M1 ieee std_logic_1164
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Efilter
w1161680596
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FD:/MATLAB7/work/hdlsrc/filter.vhd
l0
L37
V;N8@6?Z[hUgekO6d`_WjB2
OE;C;6.1f;31
32
o-work work -2002 -explicit
tExplicit 1 GenerateLoopIterationMax 100000
Artl
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work filter ;N8@6?Z[hUgekO6d`_WjB2
l232
L51
V8h6=8eoI0_;]dGQT1C<Um3
OE;C;6.1f;31
32
M2 ieee std_logic_1164
M1 ieee numeric_std
o-work work -2002 -explicit
tExplicit 1 GenerateLoopIterationMax 100000
Efilter_tb
w1161680597
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FD:/MATLAB7/work/hdlsrc/filter_tb.vhd
l0
L37
V[cJ=:FceDd[^^1QGf6ehH3
OE;C;6.1f;31
32
o-work work -2002 -explicit
tExplicit 1 GenerateLoopIterationMax 100000
Atest
DE work filter ;N8@6?Z[hUgekO6d`_WjB2
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work filter_tb [cJ=:FceDd[^^1QGf6ehH3
l370
L43
V`7A18jdRA5Dkfe;YW`;F22
OE;C;6.1f;31
32
M2 ieee std_logic_1164
M1 ieee numeric_std
o-work work -2002 -explicit
tExplicit 1 GenerateLoopIterationMax 100000
Pmy_vhdl_1234
w1147878472
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/HDL/pic_combine.vhd
l0
L21
Vc4iT13CO_O6X_b5G8`SV@1
OE;C;6.1f;31
32
b1
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Bbody
DB work my_vhdl_1234 c4iT13CO_O6X_b5G8`SV@1
l0
L21
VDMiICd2bPkBTKVKCgm`2Z3
OE;C;6.1f;31
32
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
nbody
Enandgate
w1143711802
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/HDL/Nandgate.vhd
l0
L4
V]Db3T8HN6HXlk^hIbWa333
OE;C;6.1f;31
32
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Anandgate1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work nandgate ]Db3T8HN6HXlk^hIbWa333
l12
L11
Vm^az=8fO_8FPQmm3aO[SE1
OE;C;6.1f;31
32
M1 ieee std_logic_1164
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Epic12c5xx
w1147878472
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/HDL/pic_combine.vhd
l0
L15
V4>ULWABi`U8E]EJ4C<oJf0
OE;C;6.1f;31
32
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Apic12c5xx1
DP work my_vhdl_1234 ;h2^17bJB>Z]=DQm7PcAh1
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work pic12c5xx 6zh6Sz@z:QRY5jUbfXcmN0
l38
L26
VQ0WGO:ldNfebcGPbjWMQ_2
OE;C;6.1f;31
32
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 work my_vhdl_1234
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/HDL/Code18_05_06.vhd
w1157636886
Eprogram_counter
w1147878472
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/HDL/pic_combine.vhd
l0
L11
VL2ai^n_7]`9=:^HIEKVj<1
OE;C;6.1f;31
32
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Erom
w1147878472
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/HDL/pic_combine.vhd
l0
L7
VC23PTH_GfA?7FQ;WX=VEa0
OE;C;6.1f;31
32
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Ctest_decoder_behavioural
adecoder_3_8
etestbench
DE work decoder 4WkihchEoi9ZE_::GGOSA0
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DA work testbench decoder_3_8 5@K;Ai?ac9:V3lJg8MR<@2
DE work testbench an@0Mh4T<0ji95LEPFINf1
w1143107238
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/HDL/Testbench_decoder.vhd
l0
L0
V[T`TZiEbZXG<0kC]_9kW13
OE;C;6.1f;31
32
M1 ieee std_logic_1164
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Ctest_decoder_structural
adecoder_3_8
etestbench
DE work decoder 4WkihchEoi9ZE_::GGOSA0
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DA work testbench decoder_3_8 5@K;Ai?ac9:V3lJg8MR<@2
DE work testbench an@0Mh4T<0ji95LEPFINf1
w1143107238
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/HDL/Testbench_decoder.vhd
l0
L0
V:Yd[mH<>:<OVl]Cfj:G9]1
OE;C;6.1f;31
32
M1 ieee std_logic_1164
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Etestbench
w1143107238
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/HDL/Testbench_decoder.vhd
l0
L1
Van@0Mh4T<0ji95LEPFINf1
OE;C;6.1f;31
32
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Adecoder_3_8
DE work testbench an@0Mh4T<0ji95LEPFINf1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
l65
L9
V5@K;Ai?ac9:V3lJg8MR<@2
OE;C;6.1f;31
32
M1 ieee std_logic_1164
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Etlc
w1157546720
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/Lab3&4/lab4/tlc.vhd
l0
L4
V=gRc@27eZ=OXiZL0>27@h0
OE;C;6.1f;31
32
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Atlc1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work tlc =gRc@27eZ=OXiZL0>27@h0
l16
L12
Vg=ge[c7V5TYK86W=W1OO10
OE;C;6.1f;31
32
M1 ieee std_logic_1164
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Etraffic
w1157546845
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\Assignment\Semester 4\EEET1256 Digital Design Automation\Lab3&4\lab4
FE:/Assignment/Semester 4/EEET1256 Digital Design Automation/Lab3&4/lab4/traffic.vhd
l0
L4
VGXUUm;YbdNl@ROj>H7Eck2
OE;C;6.1f;31
32
o-work work
tExplicit 1 GenerateLoopIterationMax 100000
Atraffic1
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work traffic GXUUm;YbdNl@ROj>H7Eck2
l16
L12
VHA286TX9_[]`W0I4C:Od60
OE;C;6.1f;31
32
M1 ieee std_logic_1164
o-work work
tExplicit 1 GenerateLoopIterationMax 100000