uarttest.hif

《FPGA嵌入式应用系统开发典型实例》-书的光盘资料

HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	clk_pdiv.tdf
	{
		clk_pdiv [WIDTH=1,USE_LPM_FOR_AHDL_OPERATORS] []
		{
			10 [WIDTH=17,USE_LPM_FOR_AHDL_OPERATORS=OFF] [out,clk,d16,d15,d14,d13,d12,d11,d10,d9,d8,d7,d6,d5,d4,d3,d2,d1,d0,reset];
		}
	}
	lpm_dff.tdf
	{
		lpm_dff [DEVICE_FAMILY,LPM_SVALUE=0,LPM_AVALUE=0,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [lpm_constant.inc,dffeea.inc,aglobal.inc]
		{
			5 [DEVICE_FAMILY=FLEX6000,LPM_SVALUE=0,LPM_AVALUE=0,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [q7,q6,q5,q4,q3,q2,q1,q0,data7,data6,data5,data4,data3,data2,data1,data0,clock,enable,shiftin,shiften,aclr];
			4 [DEVICE_FAMILY=FLEX6000,LPM_SVALUE=0,LPM_AVALUE=0,LPM_WIDTH=5,USE_LPM_FOR_AHDL_OPERATORS=OFF] [q4,q3,q2,q1,q0,data4,data3,data2,data1,data0,clock,enable,aclr];
			3 [DEVICE_FAMILY=FLEX6000,LPM_SVALUE=0,LPM_AVALUE=0,LPM_WIDTH=8,USE_LPM_FOR_AHDL_OPERATORS=OFF] [q7,q6,q5,q4,q3,q2,q1,q0,data7,data6,data5,data4,data3,data2,data1,data0,clock,enable,aclr];
		}
	}
	rx.tdf
	{
		rx [FILTER_DEPTH,USE_LPM_FOR_AHDL_OPERATORS] [lpm_dff.inc,lpm_mux.inc,lpm_bustri.inc,lpm_counter.inc,filterx.inc,clk_pdiv.inc,par_gen.inc]
		{
			9 [FILTER_DEPTH=3,USE_LPM_FOR_AHDL_OPERATORS=OFF] [CfgReg0,CfgReg1,CfgReg2,CfgReg3,CfgReg4,CfgReg5,CfgReg6,RxSTATUS0,RxSTATUS1,RxSTATUS2,RxSTATUS3,RxSTATUS4,/RxRTS,/RxDTR,/CtrlRTS,/CtrlDTR,CLK,/DTR,/RTS,DIVISOR0,DIVISOR1,DIVISOR2,DIVISOR3,DIVISOR4,DIVISOR5,DIVISOR6,DIVISOR7,DIVISOR8,DIVISOR9,DIVISOR10,DIVISOR11,DIVISOR12,DIVISOR13,DIVISOR14,DIVISOR15,DIVISOR16,RxReg0,RxReg1,RxReg2,RxReg3,RxReg4,RxReg5,RxReg6,RxReg7,RxStart,RxEND,RESET,Rx];
		}
	}
	uart.gdf
	{
		uart [EMBEDDED,FCLK,FILTER_DEPTH] []
		{
			8 [EMBEDDED=NO,FCLK=40000000,FILTER_DEPTH=3] [];
		}
	}
	uarttest.gdf
	{
		uarttest [] []
		{
			0 [] [];
		}
	}
}
TREE
{
	uarttest::(0,0):(0): uarttest.gdf
	{
		uart::(0,0):(1): uart.gdf
		{
			rx:9:(0,0):(4): rx.tdf
			{
				lpm_dff:3:(147,13):(75): lpm_dff.tdf;
				lpm_dff:4:(150,19):(104): lpm_dff.tdf;
				lpm_dff:5:(153,13):(127): lpm_dff.tdf;
				clk_pdiv:10:(156,13):(156): clk_pdiv.tdf;
				lpm_dff::(159,12):(196): lpm_dff.tdf;
				filterx::(162,10):(211): filterx.tdf;
				lpm_counter::(165,13):(220): lpm_counter.tdf;
				par_gen::(168,12):(260): par_gen.tdf;
				lpm_dff::(171,13):(271): lpm_dff.tdf;
			}
			tx::(0,0):(5): tx.tdf;
			uartctrl::(0,0):(31): uartctrl.tdf;
		}
	}
}