filter.vhd

《FPGA嵌入式应用系统开发典型实例》-书的光盘资料

-- -------------------------------------------------------------
--
-- Module: filter
--
-- Generated by MATLAB(R) 7.0 and the Filter Design HDL Coder 1.0.
--
-- Generated on: 2004-12-22 12:33:35
--
-- -------------------------------------------------------------

-- ------------------------------------------------------------- -- HDL Code 
Generation Options: -- -- TargetLanguage: VHDL -- LoopUnrolling: On --
PackagePostfix: -- SplitEntityFilePostfix: -- SplitArchFilePostfix: --
InlineConfigurations: Off -- SafeZeroConcat: Off -- TestBenchStimulus: impulse 
step ramp chirp noise -- -- Filter Settings: -- -- Discrete-Time FIR Filter 
(real) -- ------------------------------- -- Filter Structure  : Direct-Form FIR 
-- Filter Order      : 14 -- Stable            : Yes -- Linear Phase      : Yes 
(Type 2) -- Arithmetic        : fixed -- --          CoeffWordLength: 16 --
CoeffAutoScale: true --                   Signed: true -- --
InputWordLength: 16 --          InputFracLength: 15 -- --
OutputWordLength: 16 --               OutputMode: 'AvoidOverflow' -- --
ProductMode: 'FullPrecision' -- --                AccumMode: 'KeepMSB' --
AccumWordLength: 40 --            CastBeforeSum: true -- --
RoundMode: 'convergent' --             OverflowMode: 'wrap' -- -----------------
-------------------------------------------- LIBRARY IEEE; USE 
IEEE.std_logic_1164.all; USE IEEE.numeric_std.ALL;

ENTITY filter IS
   PORT( clk                             :   IN    std_logic; 
         clk_enable                      :   IN    std_logic; 
         reset                           :   IN    std_logic; 
         filter_in                       :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
         filter_out                      :   OUT   std_logic_vector(15 DOWNTO 0)  -- sfix16_En9
         );

END filter;


----------------------------------------------------------------
--Module Architecture: filter
----------------------------------------------------------------
ARCHITECTURE rtl OF filter IS
  -- Local Functions
  -- Type Definitions
  TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF signed(15 DOWNTO 0); -- sfix16_En15
  -- Constants
  CONSTANT coeff1    : signed(15 DOWNTO 0) := to_signed(0, 16); -- sfix16_En14
  CONSTANT coeff2    : signed(15 DOWNTO 0) := to_signed(1948, 16); -- sfix16_En14
  CONSTANT coeff3    : signed(15 DOWNTO 0) := to_signed(1442, 16); -- sfix16_En14
  CONSTANT coeff4    : signed(15 DOWNTO 0) := to_signed(-1781, 16); -- sfix16_En14
  CONSTANT coeff5    : signed(15 DOWNTO 0) := to_signed(-3738, 16); -- sfix16_En14
  CONSTANT coeff6    : signed(15 DOWNTO 0) := to_signed(0, 16); -- sfix16_En14
  CONSTANT coeff7    : signed(15 DOWNTO 0) := to_signed(8818, 16); -- sfix16_En14
  CONSTANT coeff8    : signed(15 DOWNTO 0) := to_signed(16384, 16); -- sfix16_En14
  CONSTANT coeff9    : signed(15 DOWNTO 0) := to_signed(16384, 16); -- sfix16_En14
  CONSTANT coeff10   : signed(15 DOWNTO 0) := to_signed(8818, 16); -- sfix16_En14
  CONSTANT coeff11   : signed(15 DOWNTO 0) := to_signed(0, 16); -- sfix16_En14
  CONSTANT coeff12   : signed(15 DOWNTO 0) := to_signed(-3738, 16); -- sfix16_En14
  CONSTANT coeff13   : signed(15 DOWNTO 0) := to_signed(-1781, 16); -- sfix16_En14
  CONSTANT coeff14   : signed(15 DOWNTO 0) := to_signed(1442, 16); -- sfix16_En14
  CONSTANT coeff15   : signed(15 DOWNTO 0) := to_signed(1948, 16); -- sfix16_En14
  CONSTANT coeff16   : signed(15 DOWNTO 0) := to_signed(0, 16); -- sfix16_En14

  -- Signals
  SIGNAL delay_pipeline     : delay_pipeline_type(0 TO 15); -- sfix16_En15
  SIGNAL product15          : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL product14          : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL product13          : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL product12          : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL product10          : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL product9           : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL product8           : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL product7           : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL product5           : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL product4           : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL product3           : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL product2           : signed(31 DOWNTO 0); -- sfix32_En29
  SIGNAL sum1               : signed(39 DOWNTO 0); -- sfix40_En29
  SIGNAL add_temp           : signed(32 DOWNTO 0); -- sfix33_En29
  SIGNAL sum2               : signed(39 DOWNTO 0); -- sfix40_En29
  SIGNAL add_temp_1         : signed(40 DOWNTO 0); -- sfix41_En29
  SIGNAL sum3               : signed(39 DOWNTO 0); -- sfix40_En29
  SIGNAL add_temp_2         : signed(40 DOWNTO 0); -- sfix41_En29
  SIGNAL sum4               : signed(39 DOWNTO 0); -- sfix40_En29
  SIGNAL add_temp_3         : signed(40 DOWNTO 0); -- sfix41_En29
  SIGNAL sum5               : signed(39 DOWNTO 0); -- sfix40_En29
  SIGNAL add_temp_4         : signed(40 DOWNTO 0); -- sfix41_En29
  SIGNAL sum6               : signed(39 DOWNTO 0); -- sfix40_En29
  SIGNAL add_temp_5         : signed(40 DOWNTO 0); -- sfix41_En29
  SIGNAL sum7               : signed(39 DOWNTO 0); -- sfix40_En29
  SIGNAL add_temp_6         : signed(40 DOWNTO 0); -- sfix41_En29
  SIGNAL sum8               : signed(39 DOWNTO 0); -- sfix40_En29
  SIGNAL add_temp_7         : signed(40 DOWNTO 0); -- sfix41_En29
  SIGNAL sum9               : signed(39 DOWNTO 0); -- sfix40_En29
  SIGNAL add_temp_8         : signed(40 DOWNTO 0); -- sfix41_En29
  SIGNAL sum10              : signed(39 DOWNTO 0); -- sfix40_En29
  SIGNAL add_temp_9         : signed(40 DOWNTO 0); -- sfix41_En29
  SIGNAL sum11              : signed(39 DOWNTO 0); -- sfix40_En29
  SIGNAL add_temp_10        : signed(40 DOWNTO 0); -- sfix41_En29
  SIGNAL output_typeconvert : signed(15 DOWNTO 0); -- sfix16_En9
  SIGNAL output_register    : signed(15 DOWNTO 0); -- sfix16_En9


BEGIN

  -- Block Statements
  Delay_Pipeline_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      delay_pipeline(0 TO 15) <= (OTHERS => (OTHERS => '0'));
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        delay_pipeline(0) <= signed(filter_in);
        delay_pipeline(1 TO 15) <= delay_pipeline(0 TO 14);
      END IF;
    END IF; 
  END PROCESS Delay_Pipeline_process;

  product15 <= delay_pipeline(14) * coeff15;

  product14 <= delay_pipeline(13) * coeff14;

  product13 <= delay_pipeline(12) * coeff13;

  product12 <= delay_pipeline(11) * coeff12;

  product10 <= delay_pipeline(9) * coeff10;

  product9 <= resize( delay_pipeline(8)(15 DOWNTO 0) & "00000000000000", 32);

  product8 <= resize( delay_pipeline(7)(15 DOWNTO 0) & "00000000000000", 32);

  product7 <= delay_pipeline(6) * coeff7;

  product5 <= delay_pipeline(4) * coeff5;

  product4 <= delay_pipeline(3) * coeff4;

  product3 <= delay_pipeline(2) * coeff3;

  product2 <= delay_pipeline(1) * coeff2;

  add_temp <= resize(product2, 33) + resize(product3, 33);
  sum1 <= resize( add_temp, 40);

  add_temp_1 <= resize(sum1, 41) + resize(product4, 41);
  sum2 <= add_temp_1(39 DOWNTO 0);

  add_temp_2 <= resize(sum2, 41) + resize(product5, 41);
  sum3 <= add_temp_2(39 DOWNTO 0);

  add_temp_3 <= resize(sum3, 41) + resize(product7, 41);
  sum4 <= add_temp_3(39 DOWNTO 0);

  add_temp_4 <= resize(sum4, 41) + resize(product8, 41);
  sum5 <= add_temp_4(39 DOWNTO 0);

  add_temp_5 <= resize(sum5, 41) + resize(product9, 41);
  sum6 <= add_temp_5(39 DOWNTO 0);

  add_temp_6 <= resize(sum6, 41) + resize(product10, 41);
  sum7 <= add_temp_6(39 DOWNTO 0);

  add_temp_7 <= resize(sum7, 41) + resize(product12, 41);
  sum8 <= add_temp_7(39 DOWNTO 0);

  add_temp_8 <= resize(sum8, 41) + resize(product13, 41);
  sum9 <= add_temp_8(39 DOWNTO 0);

  add_temp_9 <= resize(sum9, 41) + resize(product14, 41);
  sum10 <= add_temp_9(39 DOWNTO 0);

  add_temp_10 <= resize(sum10, 41) + resize(product15, 41);
  sum11 <= add_temp_10(39 DOWNTO 0);

  output_typeconvert <= resize( shift_right(sum11(35 DOWNTO 0) + ( "0" & (sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20) & NOT sum11(20))), 20), 16);

  Output_Register_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      output_register <= (OTHERS => '0');
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        output_register <= output_typeconvert;
      END IF;
    END IF; 
  END PROCESS Output_Register_process;

  -- Assignment Statements
  filter_out <= std_logic_vector(output_register);

END rtl;