intigrator_fe.vhd

来自「《FPGA嵌入式应用系统开发典型实例》-书的光盘资料」· VHDL 代码 · 共 60 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

LIBRARY LPM;
USE LPM.LPM_COMPONENTS.ALL;

ENTITY INTIGRATOR_FE IS
PORT(	
		RESET:		IN	STD_LOGIC;
		CLK:		IN	STD_LOGIC;
		COS:		IN	SIGNED(7 DOWNTO 0);
		SIN:		IN	SIGNED(7 DOWNTO 0);
		COSOUT:		OUT	SIGNED(15 DOWNTO 0);
		SINOUT:		OUT	SIGNED(15 DOWNTO 0);
		AVRCLK:		OUT STD_LOGIC
	);
END INTIGRATOR_FE;

ARCHITECTURE FE_ARCH OF INTIGRATOR_FE IS
SIGNAL	COSA:	SIGNED(15 DOWNTO 0);
SIGNAL	SINA:	SIGNED(15 DOWNTO 0);
--SIGNAL	COSB:	SIGNED(15 DOWNTO 0);
--SIGNAL	SINB:	SIGNED(15 DOWNTO 0);
SIGNAL	CYCLE:	INTEGER RANGE 0 TO 255;
SIGNAL	CV:		STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
	CV <= CONV_STD_LOGIC_VECTOR(CYCLE,8);
	AVRCLK <= CV(7);
	PROCESS(RESET,CLK)
	BEGIN
		IF RESET = '0' THEN
			CYCLE <= 0;
			COSA <= (OTHERS => '0');
			SINA <= (OTHERS => '0');
--			COSB <= (OTHERS => '0');
--			SINB <= (OTHERS => '0');
		ELSE
			IF CLK'EVENT AND CLK = '1' THEN
				IF CYCLE = 255 THEN
					CYCLE <= 0;
					COSA <= (OTHERS=>'0');	--COSB + (COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS);
--					COSB <= (OTHERS => '0');
					SINA <= (OTHERS=>'0');	--SINB + (SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN);
--					SINB <= (OTHERS => '0');
					COSOUT <= COSA + (COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS);
					SINOUT <= SINA + (SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN);
				ELSE
					CYCLE <= CYCLE + 1;
--					COSB <= COSA;
					COSA <= COSA + (COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS(7)&COS);
--					SINB <= SINA;
					SINA <= SINA + (SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN(7)&SIN);
				END IF;
			END IF;
		END IF;
	END PROCESS;
END FE_ARCH;