intigrator_fe.bsf

《FPGA嵌入式应用系统开发典型实例》-书的光盘资料

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2005 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 16 16 200 144)
	(text "INTIGRATOR_FE" (rect 5 0 92 12)(font "Arial" ))
	(text "inst" (rect 8 112 25 124)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "RESET" (rect 0 0 35 12)(font "Arial" ))
		(text "RESET" (rect 21 27 56 39)(font "Arial" ))
		(line (pt 0 32)(pt 16 32)(line_width 1))
	)
	(port
		(pt 0 48)
		(input)
		(text "CLK" (rect 0 0 21 12)(font "Arial" ))
		(text "CLK" (rect 21 43 42 55)(font "Arial" ))
		(line (pt 0 48)(pt 16 48)(line_width 1))
	)
	(port
		(pt 0 64)
		(input)
		(text "COS[7..0]" (rect 0 0 49 12)(font "Arial" ))
		(text "COS[7..0]" (rect 21 59 70 71)(font "Arial" ))
		(line (pt 0 64)(pt 16 64)(line_width 3))
	)
	(port
		(pt 0 80)
		(input)
		(text "SIN[7..0]" (rect 0 0 44 12)(font "Arial" ))
		(text "SIN[7..0]" (rect 21 75 65 87)(font "Arial" ))
		(line (pt 0 80)(pt 16 80)(line_width 3))
	)
	(port
		(pt 184 32)
		(output)
		(text "COSOUT[15..0]" (rect 0 0 77 12)(font "Arial" ))
		(text "COSOUT[15..0]" (rect 86 27 163 39)(font "Arial" ))
		(line (pt 184 32)(pt 168 32)(line_width 3))
	)
	(port
		(pt 184 48)
		(output)
		(text "SINOUT[15..0]" (rect 0 0 73 12)(font "Arial" ))
		(text "SINOUT[15..0]" (rect 90 43 163 55)(font "Arial" ))
		(line (pt 184 48)(pt 168 48)(line_width 3))
	)
	(port
		(pt 184 64)
		(output)
		(text "AVRCLK" (rect 0 0 43 12)(font "Arial" ))
		(text "AVRCLK" (rect 120 59 163 71)(font "Arial" ))
		(line (pt 184 64)(pt 168 64)(line_width 1))
	)
	(drawing
		(rectangle (rect 16 16 168 112)(line_width 1))
	)
)