fe_add_sel.tdf

《FPGA嵌入式应用系统开发典型实例》-书的光盘资料

SUBDESIGN FE_ADD_SEL
(
	SDC[23..0]:		INPUT;
	ADDRESS[9..0]:	OUTPUT;
)

BEGIN
	IF SDC[23..8] > 33  THEN
		ADDRESS[] = 1023;
	ELSIF SDC[23..8] > 1 AND SDC[23..8] < 34 THEN
		ADDRESS[] = SDC[13..4] + 512;
	ELSIF SDC[23..8] < 2 THEN
		ADDRESS[] = (0,SDC[8..0]);
	END IF;
END;