pn_matched_filter.tdf

《FPGA嵌入式应用系统开发典型实例》-书的光盘资料

--本程序实现扩频序列匹配滤波器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
LIBRARY LPM;
USE LPM.LPM_COMPONENTS.ALL;
ENTITY pn_matched_filter IS
PORT(	CLK:		IN STD_LOGIC;
		DECENA:	IN STD_LOGIC;
		DIN:		IN STD_LOGIC_VECTOR(5 DOWNTO 0);
		HIGH:	OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
		LOW:		OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
	);
END pn_matched_filter;

ARCHITECTURE FILTER_ARCH OF pn_matched_filter IS
TYPE REG IS ARRAY (0 TO 127) OF STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL SAMPLE: 		REG;
CONSTANT TAP_LOW: 	STD_LOGIC_VECTOR(63 DOWNTO 0) := X"50B79CACC1B5D191";
CONSTANT TAP_HIGH:	STD_LOGIC_VECTOR(63 DOWNTO 0) := X"01269EE1FC76297D";	BEGIN
	PROCESS(CLK,DECENA,SAMPLE)
	VARIABLE S_HIGH:	STD_LOGIC_VECTOR(11 DOWNTO 0);
	VARIABLE S_LOW:	STD_LOGIC_VECTOR(11 DOWNTO 0);
	VARIABLE P_HIGH:	STD_LOGIC_VECTOR(5 DOWNTO 0);
	VARIABLE P_LOW:	STD_LOGIC_VECTOR(5 DOWNTO 0);
	BEGIN
	IF CLK'EVENT AND CLK='1' THEN
		IF DECENA = '1' THEN
			SAMPLE(0) <= DIN;
			FOR I IN 1 TO 127 LOOP
				SAMPLE(I) <= SAMPLE(I-1);
			END LOOP;
			FOR I IN 0 TO 63 LOOP
				IF TAP_HIGH(I)='1' THEN
					P_HIGH := SAMPLE(2*I+1);
				ELSE
					P_HIGH := (NOT SAMPLE(2*I+1)) + '1';
				END IF;
		
				IF TAP_LOW(I) = '1' THEN
					P_LOW := SAMPLE(2*I+1);
				ELSE
					P_LOW :=(NOT SAMPLE(2*I+1)) + '1';
				END IF;
		
				IF I=0 THEN
					S_HIGH := (P_HIGH(5)&P_HIGH(5)&P_HIGH(5)
									&P_HIGH(5)&P_HIGH(5)&P_HIGH(5)
									&P_HIGH(5 DOWNTO 0))；
					S_LOW := (P_LOW(5)&P_LOW(5)&P_LOW(5)&P_LOW(5)
								&P_LOW(5)&P_LOW(5)&P_LOW(5 DOWNTO 0));
				ELSE
					S_HIGH := S_HIGH + P_HIGH(5 DOWNTO 0);
					S_LOW := S_LOW + P_LOW(5 DOWNTO 0);
				END IF;	
			END LOOP;
		END IF;	
	END IF;
		HIGH <= S_HIGH;
		LOW <= S_LOW;
	END PROCESS;
END FILTER_ARCH;