📄 cc1100.lis
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0432 ; halSpiWriteReg(CCxxx0_FSCAL1, 0x00);
0432 ; halSpiWriteReg(CCxxx0_FSCAL0, 0x11);
0432 ; halSpiWriteReg(CCxxx0_FSTEST, 0x59);
0432 ; halSpiWriteReg(CCxxx0_TEST2, 0x81);
0432 ; halSpiWriteReg(CCxxx0_TEST1, 0x35);
0432 ; halSpiWriteReg(CCxxx0_TEST0, 0x0b);
0432 ; halSpiWriteReg(CCxxx0_IOCFG2, 0x24);
0432 ; halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
0432 ; halSpiWriteReg(CCxxx0_PKTCTRL1, 0x04);
0432 ; halSpiWriteReg(CCxxx0_PKTCTRL0, 0x05);
0432 ; halSpiWriteReg(CCxxx0_ADDR, 0x00);
0432 ; halSpiWriteReg(CCxxx0_PKTLEN, 0xFF);*/
0432 ;
0432 ; if(halSpiReadReg(CCxxx0_MDMCFG1)!=0x22)
0432 03E1 ldi R16,19
0434 42DF xcall _halSpiReadReg
0436 0232 cpi R16,34
0438 09F0 breq L99
043A ; goto l_setCC1100;
043A 98CF xjmp L98
043C L99:
043C L97:
043C .dbline 0 ; func end
043C 0895 ret
043E ; packetLength -> R20
043E ; SIG_INTERRUPT1 -> R20,R21
.even
043E _TOSH_SIGNAL::
043E 0E940000 xcall push_gset1
0442 A801 movw R20,R16
0444 2197 sbiw R28,1
0446 ; }
0446 ; /**************************************************/
0446 ;
0446 ; //接收到数据中断
0446 ;
0446 ; TOSH_SIGNAL(SIG_INTERRUPT1)
0446 ; {
0446 ; unsigned char packetLength;
0446 ; packetLength = halSpiReadReg(CCxxx0_RXFIFO);
0446 0FEF ldi R16,255
0448 38DF xcall _halSpiReadReg
044A 402F mov R20,R16
044C ; rxBuffer[0]=packetLength;
044C 40930100 sts _rxBuffer,R20
0450 ; if(rxBuffer[0] <= 32)
0450 80E2 ldi R24,32
0452 8017 cp R24,R16
0454 50F0 brlo L102
0456 ; {
0456 ; halSpiReadBurstReg(CCxxx0_RXFIFO, &rxBuffer[1], packetLength);
0456 4883 std y+0,R20
0458 20E0 ldi R18,<_rxBuffer+1
045A 30E0 ldi R19,>_rxBuffer+1
045C 0FEF ldi R16,255
045E 4ADF xcall _halSpiReadBurstReg
0460 ; CC1100_receive(&rxBuffer[0]);
0460 00E0 ldi R16,<_rxBuffer
0462 10E0 ldi R17,>_rxBuffer
0464 0E940000 xcall _CC1100_receive
0468 ; }
0468 02C0 xjmp L103
046A L102:
046A ; else
046A ; {
046A ; halSpiStrobe(CCxxx0_SFRX);
046A 0AE3 ldi R16,58
046C A1DE xcall _halSpiStrobe
046E ; }
046E L103:
046E ; halSpiStrobe(CCxxx0_SFRX);
046E 0AE3 ldi R16,58
0470 9FDE xcall _halSpiStrobe
0472 ; halSpiStrobe(CCxxx0_SRX);
0472 04E3 ldi R16,52
0474 9DDE xcall _halSpiStrobe
0476 L101:
0476 2196 adiw R28,1
0478 0E940000 xcall pop_gset1
047C .dbline 0 ; func end
047C 0895 ret
047E ; nnn -> R20,R21
.even
047E _CC1100_init::
047E 0E940000 xcall push_gset1
0482 2197 sbiw R28,1
0484 ; }
0484 ; /**************************************************/
0484 ; //初始化
0484 ; uint8_t CC1100_init()
0484 ; {
0484 ; uint16_t nnn;
0484 ; SET_CSN();
0484 D5DD xcall _SET_CSN
0486 ; CLEAR_CLOCK();
0486 C2DD xcall _CLEAR_CLOCK
0488 ; CLEAR_IN();
0488 CDDD xcall _CLEAR_IN
048A ;
048A ; CC1100_setInterrupt(0x00);
048A 0027 clr R16
048C 1127 clr R17
048E 54D0 xcall _CC1100_setInterrupt
0490 ; CC1100_POR();
0490 C3DE xcall _CC1100_POR
0492 4427 clr R20
0494 5527 clr R21
0496 02C0 xjmp L109
0498 L106:
0498 L107:
0498 4F5F subi R20,255 ; offset = 1
049A 5F4F sbci R21,255
049C L109:
049C ; for(nnn=0;nnn<500;nnn++);
049C 443F cpi R20,244
049E E1E0 ldi R30,1
04A0 5E07 cpc R21,R30
04A2 D0F3 brlo L106
04A4 ; halRfWriteRfSettings();
04A4 63DF xcall _halRfWriteRfSettings
04A6 ; halSpiWriteBurstReg(CCxxx0_PATABLE, paTable, sizeof(paTable));
04A6 88E0 ldi R24,8
04A8 8883 std y+0,R24
04AA 20E0 ldi R18,<_paTable
04AC 30E0 ldi R19,>_paTable
04AE 0EE3 ldi R16,62
04B0 8FDE xcall _halSpiWriteBurstReg
04B2 ;
04B2 ; CC1100_setInterrupt(0x00);
04B2 0027 clr R16
04B4 1127 clr R17
04B6 40D0 xcall _CC1100_setInterrupt
04B8 ; CC1100_setStrobe(CCxxx0_SIDLE);
04B8 06E3 ldi R16,54
04BA 10E0 ldi R17,0
04BC 05D0 xcall _CC1100_setStrobe
04BE ; return 1;
04BE 01E0 ldi R16,1
04C0 L105:
04C0 2196 adiw R28,1
04C2 0E940000 xcall pop_gset1
04C6 .dbline 0 ; func end
04C6 0895 ret
04C8 ; state -> R20
.even
04C8 _CC1100_setStrobe::
04C8 0E940000 xcall push_gset1
04CC 402F mov R20,R16
04CE ; }
04CE ; //设置状态
04CE ; uint8_t CC1100_setStrobe(uint8_t state)
04CE ; {
04CE ; halSpiStrobe(state);
04CE 042F mov R16,R20
04D0 6FDE xcall _halSpiStrobe
04D2 ; Dly1mS(5);
04D2 05E0 ldi R16,5
04D4 10E0 ldi R17,0
04D6 D0DD xcall _Dly1mS
04D8 ; return 1;
04D8 01E0 ldi R16,1
04DA L110:
04DA 0E940000 xcall pop_gset1
04DE .dbline 0 ; func end
04DE 0895 ret
04E0 ; value -> R22
04E0 ; address -> R20
.even
04E0 _CC1100_setRegister::
04E0 0E940000 xcall push_gset2
04E4 622F mov R22,R18
04E6 402F mov R20,R16
04E8 ; }
04E8 ; //写寄存器
04E8 ; uint8_t CC1100_setRegister(uint8_t address,uint8_t value)
04E8 ; {
04E8 ; halSpiWriteReg(address,value);
04E8 262F mov R18,R22
04EA 042F mov R16,R20
04EC 4DDE xcall _halSpiWriteReg
04EE ; return 1;
04EE 01E0 ldi R16,1
04F0 L111:
04F0 0E940000 xcall pop_gset2
04F4 .dbline 0 ; func end
04F4 0895 ret
04F6 ; address -> R20
.even
04F6 _CC1100_readRegister::
04F6 0E940000 xcall push_gset1
04FA 402F mov R20,R16
04FC ; }
04FC ; //读寄存器
04FC ; uint8_t CC1100_readRegister(uint8_t address)
04FC ; {
04FC ; rd_reg = halSpiReadReg(address);
04FC 042F mov R16,R20
04FE DDDE xcall _halSpiReadReg
0500 00930000 sts _rd_reg,R16
0504 ; return rd_reg;
0504 L112:
0504 0E940000 xcall pop_gset1
0508 .dbline 0 ; func end
0508 0895 ret
050A ; address -> R20
.even
050A _CC1100_readStatus::
050A 0E940000 xcall push_gset1
050E 402F mov R20,R16
0510 ; }
0510 ; //读状态
0510 ; uint8_t CC1100_readStatus(uint8_t address)
0510 ; {
0510 ; return halSpiReadStatus(address);
0510 042F mov R16,R20
0512 18DF xcall _halSpiReadStatus
0514 L113:
0514 0E940000 xcall pop_gset1
0518 .dbline 0 ; func end
0518 0895 ret
051A ; count -> y+5
051A ; buffer -> R22,R23
051A ; addr -> R20
.even
051A _CC1100_readBurstReg::
051A 0E940000 xcall push_gset2
051E B901 movw R22,R18
0520 402F mov R20,R16
0522 2197 sbiw R28,1
0524 ;
0524 ; }
0524 ; //连续读
0524 ; uint8_t CC1100_readBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
0524 ; {
0524 ; halSpiReadBurstReg(addr, buffer, count);
0524 0D80 ldd R0,y+5
0526 0882 std y+0,R0
0528 9B01 movw R18,R22
052A 042F mov R16,R20
052C E3DE xcall _halSpiReadBurstReg
052E ; return 1;
052E 01E0 ldi R16,1
0530 L114:
0530 2196 adiw R28,1
0532 0E940000 xcall pop_gset2
0536 .dbline 0 ; func end
0536 0895 ret
0538 ; flag -> R20
.even
0538 _CC1100_setInterrupt::
0538 0E940000 xcall push_gset1
053C 402F mov R20,R16
053E ; }
053E ; //halSpiReadStatus
053E ; //设置中断
053E ; uint8_t CC1100_setInterrupt(uint8_t flag)
053E ; {
053E ; if(flag==0x00)
053E 4423 tst R20
0540 49F4 brne L116
0542 ; {
0542 ; EIFR=0x02;EICRA=0x08;EICRB=0x00;EIMSK=0x00;
0542 82E0 ldi R24,2
0544 88BF out 0x38,R24
0546 88E0 ldi R24,8
0548 80936A00 sts 106,R24
054C 2224 clr R2
054E 2ABE out 0x3a,R2
0550 29BE out 0x39,R2
0552 ; }
0552 12C0 xjmp L117
0554 L116:
0554 ; else if(flag==0x01)
0554 4130 cpi R20,1
0556 61F4 brne L118
0558 ; {
0558 ; EIFR=0x02;EICRA=0x08;EICRB=0x00;EIMSK=0x02;
0558 82E0 ldi R24,2
055A 88BF out 0x38,R24
055C 88E0 ldi R24,8
055E 80936A00 sts 106,R24
0562 2224 clr R2
0564 2ABE out 0x3a,R2
0566 82E0 ldi R24,2
0568 89BF out 0x39,R24
056A ; halSpiStrobe(CCxxx0_SRX);
056A 04E3 ldi R16,52
056C 21DE xcall _halSpiStrobe
056E ; }
056E 04C0 xjmp L119
0570 L118:
0570 ; else if(flag==0x02)
0570 4230 cpi R20,2
0572 11F4 brne L120
0574 ; {
0574 ; halSpiStrobe(CCxxx0_SRX);
0574 04E3 ldi R16,52
0576 1CDE xcall _halSpiStrobe
0578 ; }
0578 L120:
0578 L119:
0578 L117:
0578 ; return 1;
0578 01E0 ldi R16,1
057A L115:
057A 0E940000 xcall pop_gset1
057E .dbline 0 ; func end
057E 0895 ret
0580 ; size -> R22
0580 ; txPtr -> R20,R21
.even
0580 _CC1100_sendRFburst::
0580 0E940000 xcall push_gset2
0584 622F mov R22,R18
0586 A801 movw R20,R16
0588 ; }
0588 ; //连续发
0588 ; uint8_t CC1100_sendRFburst(uint8_t *txPtr,uint8_t size)
0588 ; {
0588 ; CC1100_setInterrupt(0x00); //关中断
0588 0027 clr R16
058A D6DF xcall _CC1100_setInterrupt
058C ; halSpiStrobe(CCxxx0_SIDLE);
058C 06E3 ldi R16,54
058E 10DE xcall _halSpiStrobe
0590 ; halRfSendPacket(txPtr, size);
0590 262F mov R18,R22
0592 8A01 movw R16,R20
0594 6FDE xcall _halRfSendPacket
0596 ; //Dly1mS(100);
0596 ; if(SEND_DONE==0x01) //表明发送完成
0596 80910800 lds R24,_SEND_DONE
059A 8130 cpi R24,1
059C 49F4 brne L123
059E ; {
059E ; SEND_DONE=0x00;
059E 2224 clr R2
05A0 20920800 sts _SEND_DONE,R2
05A4 ; CC1100_sendDone(1);
05A4 01E0 ldi R16,1
05A6 10E0 ldi R17,0
05A8 0E940000 xcall _CC1100_sendDone
05AC ; CC1100_setInterrupt(0x01); //开中断
05AC 01E0 ldi R16,1
05AE C4DF xcall _CC1100_setInterrupt
05B0 ; }
05B0 L123:
05B0 ; return 1;
05B0 01E0 ldi R16,1
05B2 L122:
05B2 0E940000 xcall pop_gset2
05B6 .dbline 0 ; func end
05B6 0895 ret
.area bss(ram, con, rel)
0000 _rd_reg::
0000 .blkb 1
0001 _rxBuffer::
0001 .blkb 32
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