📄 cc1100.lis
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0336 ; halRfSendPacket(txBuffer_CCxx00, sizeof(txBuffer_CCxx00));
0336 ; Dly1mS(100);
0336 ; }
0336 ; */
0336 ; /*********************************************************/
0336 ; unsigned char halSpiReadReg(unsigned char addr)
0336 ; {
0336 ; unsigned char value;
0336 ; CLEAR_CLOCK();
0336 80916500 lds R24,101
033A 8E7F andi R24,254
033C 80936500 sts 101,R24
0340 ; Dly10us();Dly10us();
0340 72DE xcall _Dly10us
0342 71DE xcall _Dly10us
0344 ; CLEAR_CSN(); // CSn=0
0344 AA98 cbi 0x15,2
0346 ; addr|=READ_SINGLE;
0346 4068 ori R20,128
0348 ; SPI_write(addr);
0348 042F mov R16,R20
034A 9CDE xcall _SPI_write
034C ; CLEAR_IN();
034C 80916500 lds R24,101
0350 8D7F andi R24,253
0352 80936500 sts 101,R24
0356 ; Dly10us();Dly10us();Dly10us();Dly10us();Dly10us();
0356 67DE xcall _Dly10us
0358 66DE xcall _Dly10us
035A 65DE xcall _Dly10us
035C 64DE xcall _Dly10us
035E 63DE xcall _Dly10us
0360 ; value=0;
0360 4427 clr R20
0362 ; value=SPI_read();
0362 D2DE xcall _SPI_read
0364 402F mov R20,R16
0366 ; Dly10us();Dly10us();Dly10us();
0366 5FDE xcall _Dly10us
0368 5EDE xcall _Dly10us
036A 5DDE xcall _Dly10us
036C ; CLEAR_CLOCK();
036C 80916500 lds R24,101
0370 8E7F andi R24,254
0372 80936500 sts 101,R24
0376 ; CLEAR_IN();
0376 80916500 lds R24,101
037A 8D7F andi R24,253
037C 80936500 sts 101,R24
0380 ; SET_CSN(); // CSn=0 P_CSn=0;
0380 AA9A sbi 0x15,2
0382 ; return value;
0382 042F mov R16,R20
0384 L81:
0384 0E940000 xcall pop_gset1
0388 .dbline 0 ; func end
0388 0895 ret
038A ; value -> R20
038A ; i -> R22
038A ; count -> R10
038A ; buffer -> R12,R13
038A ; addr -> R20
.even
038A _halSpiReadBurstReg::
038A 0E940000 xcall push_gset4
038E 6901 movw R12,R18
0390 402F mov R20,R16
0392 A884 ldd R10,y+8
0394 ; }
0394 ; /**************************************************/
0394 ; void halSpiReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
0394 ; {
0394 ; unsigned char i,value;
0394 ; CLEAR_CLOCK();
0394 80916500 lds R24,101
0398 8E7F andi R24,254
039A 80936500 sts 101,R24
039E ; Dly10us();Dly10us();
039E 43DE xcall _Dly10us
03A0 42DE xcall _Dly10us
03A2 ; CLEAR_CSN(); // CSn=0 P_CSn=0;
03A2 AA98 cbi 0x15,2
03A4 ; addr|=READ_BURST;
03A4 406C ori R20,192
03A6 ; SPI_write(addr);
03A6 042F mov R16,R20
03A8 6DDE xcall _SPI_write
03AA ; CLEAR_IN();
03AA 80916500 lds R24,101
03AE 8D7F andi R24,253
03B0 80936500 sts 101,R24
03B4 ; Dly10us();Dly10us();Dly10us();Dly10us();Dly10us();
03B4 38DE xcall _Dly10us
03B6 37DE xcall _Dly10us
03B8 36DE xcall _Dly10us
03BA 35DE xcall _Dly10us
03BC 34DE xcall _Dly10us
03BE ; value=0;
03BE 4427 clr R20
03C0 ; for(i=0;i<count;i++)
03C0 6627 clr R22
03C2 08C0 xjmp L86
03C4 L83:
03C4 A1DE xcall _SPI_read
03C6 402F mov R20,R16
03C8 E62F mov R30,R22
03CA FF27 clr R31
03CC EC0D add R30,R12
03CE FD1D adc R31,R13
03D0 4083 std z+0,R20
03D2 L84:
03D2 6395 inc R22
03D4 L86:
03D4 6A15 cp R22,R10
03D6 B0F3 brlo L83
03D8 ; {
03D8 ; value=SPI_read();
03D8 ; buffer[i]=value;
03D8 ; }
03D8 ; Dly10us();Dly10us();Dly10us();
03D8 26DE xcall _Dly10us
03DA 25DE xcall _Dly10us
03DC 24DE xcall _Dly10us
03DE ; CLEAR_CLOCK();
03DE 80916500 lds R24,101
03E2 8E7F andi R24,254
03E4 80936500 sts 101,R24
03E8 ; CLEAR_IN();
03E8 80916500 lds R24,101
03EC 8D7F andi R24,253
03EE 80936500 sts 101,R24
03F2 ; SET_CSN(); // CSn=0 P_CSn=0;
03F2 AA9A sbi 0x15,2
03F4 L82:
03F4 0E940000 xcall pop_gset4
03F8 .dbline 0 ; func end
03F8 0895 ret
03FA ; rd_pin -> <dead>
03FA ; value -> R22
03FA ; addr -> R20
.even
03FA _halSpiReadStatus::
03FA 0E940000 xcall push_gset2
03FE 402F mov R20,R16
0400 ; }
0400 ; /**************************************************/
0400 ; unsigned char halSpiReadStatus(unsigned char addr)
0400 ; {
0400 ; unsigned char value,rd_pin;
0400 ; CLEAR_CSN(); // CSn=0 P_CSn=0;
0400 AA98 cbi 0x15,2
0402 L88:
0402 L89:
0402 ; while(GET_OUT());
0402 FEDD xcall _GET_OUT
0404 0030 cpi R16,0
0406 0107 cpc R16,R17
0408 E1F7 brne L88
040A X6:
040A ; CLEAR_CLOCK(); //SCLK=0 //P_SCLK=0;
040A 80916500 lds R24,101
040E 8E7F andi R24,254
0410 80936500 sts 101,R24
0414 ; addr|=READ_BURST;
0414 406C ori R20,192
0416 ; SPI_write(addr);
0416 042F mov R16,R20
0418 35DE xcall _SPI_write
041A ; value=SPI_read();
041A 76DE xcall _SPI_read
041C 602F mov R22,R16
041E ; CLEAR_CLOCK(); //SCLK=0 //P_SCLK=0;
041E 80916500 lds R24,101
0422 8E7F andi R24,254
0424 80936500 sts 101,R24
0428 ; CLEAR_IN(); // SI=0 P_SI=0;
0428 80916500 lds R24,101
042C 8D7F andi R24,253
042E 80936500 sts 101,R24
0432 ; SET_CSN(); //CSn=1 P_CSn=1;
0432 AA9A sbi 0x15,2
0434 ; return value;
0434 L87:
0434 0E940000 xcall pop_gset2
0438 .dbline 0 ; func end
0438 0895 ret
.even
043A _halRfWriteRfSettings::
043A ; }// halSpiReadStatus
043A ; /**************************************************/
043A ; void halRfWriteRfSettings()
043A ; {
043A L92:
043A ; l_setCC1100:
043A ; halSpiWriteReg(CCxxx0_FSCTRL1, 0x0C);
043A 2CE0 ldi R18,12
043C 0BE0 ldi R16,11
043E B0DE xcall _halSpiWriteReg
0440 ;
0440 ; halSpiWriteReg(CCxxx0_FSCTRL0, 0x00);
0440 2227 clr R18
0442 0CE0 ldi R16,12
0444 ADDE xcall _halSpiWriteReg
0446 ; halSpiWriteReg(CCxxx0_FREQ2, 0x10);
0446 20E1 ldi R18,16
0448 0DE0 ldi R16,13
044A AADE xcall _halSpiWriteReg
044C ; halSpiWriteReg(CCxxx0_FREQ1, 0x09);
044C 29E0 ldi R18,9
044E 0EE0 ldi R16,14
0450 A7DE xcall _halSpiWriteReg
0452 ; halSpiWriteReg(CCxxx0_FREQ0, 0x7B);
0452 2BE7 ldi R18,123
0454 0FE0 ldi R16,15
0456 A4DE xcall _halSpiWriteReg
0458 ; halSpiWriteReg(CCxxx0_MDMCFG4, 0xC6);
0458 26EC ldi R18,198
045A 00E1 ldi R16,16
045C A1DE xcall _halSpiWriteReg
045E ; halSpiWriteReg(CCxxx0_MDMCFG3, 0x83);
045E 23E8 ldi R18,131
0460 01E1 ldi R16,17
0462 9EDE xcall _halSpiWriteReg
0464 ; halSpiWriteReg(CCxxx0_MDMCFG2, 0x02);
0464 22E0 ldi R18,2
0466 02E1 ldi R16,18
0468 9BDE xcall _halSpiWriteReg
046A ; halSpiWriteReg(CCxxx0_MDMCFG1, 0x22);
046A 22E2 ldi R18,34
046C 03E1 ldi R16,19
046E 98DE xcall _halSpiWriteReg
0470 ; halSpiWriteReg(CCxxx0_MDMCFG0, 0xF8);
0470 28EF ldi R18,248
0472 04E1 ldi R16,20
0474 95DE xcall _halSpiWriteReg
0476 ; halSpiWriteReg(CCxxx0_CHANNR, 0x0a);
0476 2AE0 ldi R18,10
0478 0AE0 ldi R16,10
047A 92DE xcall _halSpiWriteReg
047C ; halSpiWriteReg(CCxxx0_DEVIATN, 0x30);
047C 20E3 ldi R18,48
047E 05E1 ldi R16,21
0480 8FDE xcall _halSpiWriteReg
0482 ; halSpiWriteReg(CCxxx0_FREND1, 0x56);
0482 26E5 ldi R18,86
0484 01E2 ldi R16,33
0486 8CDE xcall _halSpiWriteReg
0488 ; halSpiWriteReg(CCxxx0_FREND0, 0x10);
0488 20E1 ldi R18,16
048A 02E2 ldi R16,34
048C 89DE xcall _halSpiWriteReg
048E ;
048E ;
048E ; halSpiWriteReg(CCxxx0_MCSM0, 0x18);
048E 28E1 ldi R18,24
0490 08E1 ldi R16,24
0492 86DE xcall _halSpiWriteReg
0494 ; halSpiWriteReg(CCxxx0_FOCCFG, 0x15);
0494 25E1 ldi R18,21
0496 09E1 ldi R16,25
0498 83DE xcall _halSpiWriteReg
049A ; halSpiWriteReg(CCxxx0_BSCFG, 0x6C);
049A 2CE6 ldi R18,108
049C 0AE1 ldi R16,26
049E 80DE xcall _halSpiWriteReg
04A0 ; halSpiWriteReg(CCxxx0_AGCCTRL2, 0x03);
04A0 23E0 ldi R18,3
04A2 0BE1 ldi R16,27
04A4 7DDE xcall _halSpiWriteReg
04A6 ; halSpiWriteReg(CCxxx0_AGCCTRL0, 0x91);
04A6 21E9 ldi R18,145
04A8 0DE1 ldi R16,29
04AA 7ADE xcall _halSpiWriteReg
04AC ; halSpiWriteReg(CCxxx0_FSCAL3, 0xA9);
04AC 29EA ldi R18,169
04AE 03E2 ldi R16,35
04B0 77DE xcall _halSpiWriteReg
04B2 ; halSpiWriteReg(CCxxx0_FSCAL2, 0x2A);
04B2 2AE2 ldi R18,42
04B4 04E2 ldi R16,36
04B6 74DE xcall _halSpiWriteReg
04B8 ; halSpiWriteReg(CCxxx0_FSCAL0, 0x0D);
04B8 2DE0 ldi R18,13
04BA 06E2 ldi R16,38
04BC 71DE xcall _halSpiWriteReg
04BE ; halSpiWriteReg(CCxxx0_FSTEST, 0x59);
04BE 29E5 ldi R18,89
04C0 09E2 ldi R16,41
04C2 6EDE xcall _halSpiWriteReg
04C4 ; halSpiWriteReg(CCxxx0_TEST2, 0x86);
04C4 26E8 ldi R18,134
04C6 0CE2 ldi R16,44
04C8 6BDE xcall _halSpiWriteReg
04CA ; halSpiWriteReg(CCxxx0_TEST1, 0x3D);
04CA 2DE3 ldi R18,61
04CC 0DE2 ldi R16,45
04CE 68DE xcall _halSpiWriteReg
04D0 ; halSpiWriteReg(CCxxx0_TEST0, 0x09);
04D0 29E0 ldi R18,9
04D2 0EE2 ldi R16,46
04D4 65DE xcall _halSpiWriteReg
04D6 ;
04D6 ;
04D6 ; halSpiWriteReg(CCxxx0_IOCFG2, 0x24);
04D6 24E2 ldi R18,36
04D8 0027 clr R16
04DA 62DE xcall _halSpiWriteReg
04DC ;
04DC ; halSpiWriteReg(CCxxx0_IOCFG0, 0x06);
04DC 26E0 ldi R18,6
04DE 02E0 ldi R16,2
04E0 5FDE xcall _halSpiWriteReg
04E2 ; halSpiWriteReg(CCxxx0_PKTCTRL1, 0x04);
04E2 24E0 ldi R18,4
04E4 07E0 ldi R16,7
04E6 5CDE xcall _halSpiWriteReg
04E8 ; halSpiWriteReg(CCxxx0_PKTCTRL0, 0x05);
04E8 25E0 ldi R18,5
04EA 08E0 ldi R16,8
04EC 59DE xcall _halSpiWriteReg
04EE ; halSpiWriteReg(CCxxx0_ADDR, 0x00);
04EE 2227 clr R18
04F0 09E0 ldi R16,9
04F2 56DE xcall _halSpiWriteReg
04F4 ;
04F4 ; halSpiWriteReg(CCxxx0_PKTLEN, 0x1F); // hejie ,接收数据长度
04F4 2FE1 ldi R18,31
04F6 06E0 ldi R16,6
04F8 53DE xcall _halSpiWriteReg
04FA ; //halSpiWriteReg(CCxxx0_PKTLEN, 0xFF);
04FA ;
04FA ; halSpiWriteReg(CCxxx0_MCSM2, 0x08); // CCxxx0_MCSM2 修改限制时间 默认为０７ 修改为００
04FA 28E0 ldi R18,8
04FC 06E1 ldi R16,22
04FE 50DE xcall _halSpiWriteReg
0500 ; //halSpiWriteReg(CCxxx0_FIFOTHR, 0x07);
0500 ;
0500 ;
0500 ; if(halSpiReadReg(CCxxx0_MDMCFG1)!=0x22){
0500 03E1 ldi R16,19
0502 16DF xcall _halSpiReadReg
0504 0232 cpi R16,34
0506 09F0 breq L93
0508 ; // led1On();
0508 ; goto l_setCC1100;
0508 98CF xjmp L92
050A L93:
050A L91:
050A .dbline 0 ; func end
050A 0895 ret
.area vector(rom, abs)
.org 8
0008 0C948602 jmp _cc1100_rx_isr
.area text(rom, con, rel)
; packetLength -> R20
.even
050C _cc1100_rx_isr::
050C 0E940000 xcall push_lset
0510 0E940000 xcall push_gset1
0514 2197 sbiw R28,1
0516 ; }
0516 ; }
0516 ; /**************************************************/
0516 ;
0516 ; //接收到数据中断
0516 ;
0516 ; #pragma interrupt_handler cc1100_rx_isr:3
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