handset.sym

This the code using PIC MCU to control

?_halSpiWriteBurstReg 2A 0 BANK0
__Hinit23 11 0 CODE
__Linit23 11 0 CODE
__Hcode_ptr 4E 0 BANK0
__Lcode_ptr 4C 0 BANK0
__S0 2100 0
__S1 A0 0
?a_halRfReceivePacket 2A 0 BANK0
_Current_key 20 0 BANK0
?a_halSpiReadReg 2D 0 BANK0
_main 6EF 0 CODE
_exit 4 0 CODE
start 4 0 CODE
?a_RxCC1100 27 0 BANK0
?a_TxCC1100 27 0 BANK0
used_code_ptr 1 0
__Hfloat_text2 39 0 CODE
__Lfloat_text2 39 0 CODE
?a_spiGetRxTxStatus 26 0 BANK0
__Brbit_0 20 FFFFFF20 BANK0
__Hrbit_0 100 FFFFFF20 BANK0
__Lrbit_0 100 FFFFFF20 BANK0
?_halRfSendPacket 28 0 BANK0
__Brbit_1 A0 FFFFFBA0 BANK1
__Hrbss_0 35 0 BANK0
__Hrbit_1 500 FFFFFBA0 BANK1
__Lrbss_0 20 0 BANK0
__Lrbit_1 500 FFFFFBA0 BANK1
__Brbit_2 A0 FFFFFBA0 BANK2
__Hrbss_1 A0 0 BANK1
__Hrbit_2 500 FFFFFBA0 BANK2
__Lrbss_1 A0 0 BANK1
__Lrbit_2 500 FFFFFBA0 BANK2
_spiGetRxTxStatus 3E2 0 CODE
__Brbit_3 A0 FFFFFBA0 BANK3
__Hrbss_2 A0 0 BANK2
__Hrbit_3 500 FFFFFBA0 BANK3
__Lrbss_2 A0 0 BANK2
__Lrbit_3 500 FFFFFBA0 BANK3
__Hrbss_3 A0 0 BANK3
__Lrbss_3 A0 0 BANK3
?a_halSpiReadBurstReg 2F 0 BANK0
__Hintcode 4 0 CODE
__Lintcode 4 0 CODE
intlevel0 4 0 CODE
intlevel1 4 0 CODE
?a_SPI_read 32 0 BANK0
?_halRfReceivePacket 29 0 BANK0
__Heeprom_data 2100 0 EEDATA
__Leeprom_data 2100 0 EEDATA
_halSpiWriteBurstReg 581 0 CODE
__Hidata_0 800 0 CODE
__Lidata_0 7EB 0 CODE
__Hrdata_0 4A 0 BANK0
__Lrdata_0 35 0 BANK0
?a_SPI_write 32 0 BANK0
?a_halSpiWriteReg 29 0 BANK0
__Hintsave_0 A0 0
__Lintsave_0 A0 0
__Hidata_1 39 0 CODE
__Lidata_1 39 0 CODE
_halRfWriteRfSettings 766 0 CODE
__Hrdata_1 A0 0 BANK1
__Lrdata_1 A0 0 BANK1
__Hidata_2 A0 0
__Hintsave A0 0
__Lidata_2 A0 0
__Lintsave A0 0
__Hintentry 4 0 CODE
_SPI_write 60A 0 CODE
__Lintentry 4 0 CODE
__Hrdata_2 A0 0 BANK2
__Lrdata_2 A0 0 BANK2
__Hidata_3 A0 0
__Lidata_3 A0 0
__Hrdata_3 A0 0 BANK3
__Lrdata_3 A0 0 BANK3
__Hnvram_1 A0 0 BANK1
__Lnvram_1 A0 0 BANK1
_halRfReceivePacket 5C2 0 CODE
_Dly1mS 4DD 0 CODE
__Bnvbit_0 4C FFFFFDEC BANK0
__Hnvbit_0 260 FFFFFDEC BANK0
__Lnvbit_0 260 FFFFFDEC BANK0
__Hnvram_2 A0 0 BANK2
__Lnvram_2 A0 0 BANK2
?_halSpiReadBurstReg 2D 0 BANK0
__Hintsave_1 A0 0
__Lintsave_1 A0 0
__Bnvbit_1 A0 FFFFFBA0 BANK1
__Hnvbit_1 500 FFFFFBA0 BANK1
__Lnvbit_1 500 FFFFFBA0 BANK1
__Hnvram_3 A0 0 BANK3
__Lnvram_3 A0 0 BANK3
?a_Dly1mS 2C 0 BANK0
__Bnvbit_2 A0 FFFFFBA0 BANK2
__Hnvbit_2 500 FFFFFBA0 BANK2
__Lnvbit_2 500 FFFFFBA0 BANK2
_dpybuffer 40 0 BANK0
__Hcode A0 0
__Lcode A0 0
__Bnvbit_3 A0 FFFFFBA0 BANK3
__Hnvbit_3 500 FFFFFBA0 BANK3
__Lnvbit_3 500 FFFFFBA0 BANK3
__Hfloat_text3 39 0 CODE
__Lfloat_text3 39 0 CODE
copy_bank0 8 0 CODE
?a_main 26 0 BANK0
__Htemp 4C 0 BANK0
__Ltemp 4A 0 BANK0
__Hinit 11 0 CODE
__Linit 4 0 CODE
__Hintsave_2 A0 0 BANK2
__Lintsave_2 A0 0 BANK2
_Statusflag 23 0 BANK0
powerup 0 0 CODE
__Htext A0 0
__Ltext A0 0
_halSpiWriteReg 3F7 0 CODE
_halSpiReadBurstReg 484 0 CODE
__Hstrings 39 0 STRING
__Lstrings 39 0 STRING
__Hstringtable 39 0 ENTRY
__Lstringtable 23 0 ENTRY
__Hintsave_3 A0 0 BANK3
__Lintsave_3 A0 0 BANK3
__Hcommon_ram A0 0
__Lcommon_ram A0 0
?a_halSpiWriteBurstReg 2C 0 BANK0
__Hpowerup 4 0 CODE
__Lpowerup 0 0 CODE
__Hvectors 39 0 CODE
__Lvectors 39 0 CODE
_SPI_read 4AF 0 CODE
__Hclrtext 23 0 CODE
__Lclrtext 13 0 CODE
copy_data 1A 0 CODE
_halSpiReadStatus 42A 0 CODE
__Hconfig 2008 0 CONFIG
__Lconfig 2007 0 CONFIG
__Hfloat_text0 39 0 CODE
__Lfloat_text0 39 0 CODE
clear_ram 16 0 CODE
__Hfloat_text4 39 0 CODE
__Lfloat_text4 39 0 CODE
string_indir 26 0 ENTRY
__H__Z12345RS_ A0 0
__L__Z12345RS_ A0 0
_rxBuffer 24 0 BANK0
_txBuffer 3D 0 BANK0
?_Dly1mS 2A 0 BANK0
_halSpiStrobe 3CD 0 CODE
_InitPIC16F72 446 0 CODE
__Hintret 4 0 CODE
__Lintret 4 0 CODE
__Hstruct 4E 0 BANK0
__Lstruct 4E 0 BANK0
_halSpiReadReg 40F 0 CODE
_POWER_UP_RESET_CC1100 6A1 0 CODE
?a_halSpiStrobe 2D 0 BANK0
_RxCC1100 462 0 CODE
_TxCC1100 547 0 CODE
_paTable 35 0 BANK0
_Keyflag 21 0 BANK0
__Hidloc 2000 0 IDLOC
__Lidloc 2000 0 IDLOC
clear_bank0 4 0 CODE
_KeyScan 653 0 CODE
__Hnvram 4C 0 BANK0
__Lnvram 4C 0 BANK0
string_table 23 0 ENTRY
_halRfSendPacket 510 0 CODE
?a_halSpiReadStatus 2D 0 BANK0
?a_POWER_UP_RESET_CC1100 27 0 BANK0
_Old_key 22 0 BANK0
code_ptr 4C 0 BANK0
?_halSpiWriteReg 28 0 BANK0
?a_halRfSendPacket 29 0 BANK0
__Hfloat_text1 39 0 CODE
__Lfloat_text1 39 0 CODE
used_btemp0 1 0
__Hpstrings 39 0 CODE
__Lpstrings 39 0 CODE
__Hend_init 13 0 CODE
__Lend_init 11 0 CODE
used_btemp1 1 0
%segments
powerup 0 7 CODE
intentry 8 71 CODE
rbit_0 100 129 BANK0
idata_0 FD6 FFF CODE
temp 4A 4B COMBANK
config 400E 400F CONFIG
nvram 4C 4D BANK0
text11 ECC FD5 CODE
text16 DDE ECB CODE
text13 D42 DDD CODE
text15 CA6 D41 CODE
text1 C14 CA5 CODE
text10 B84 C13 CODE
text7 B02 B83 CODE
text17 A8E B01 CODE
text9 A20 A8D CODE
text0 9BA A1F CODE
text2 95E 9B9 CODE
text6 908 95D CODE
text18 8C4 907 CODE
text14 88C 8C3 CODE
text4 854 88B CODE
text3 81E 853 CODE
text5 7EE 81D CODE
text12 7C4 7ED CODE
text8 79A 7C3 CODE
%locals
E:\mywork\chipcon_demo\cc1100+pa\newshouji\main.obj
fsr 4
btemp 4A 0 BANK0
status 3
E:\mywork\chipcon_demo\cc1100+pa\newshouji\CC1100LIB.C
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E:\mywork\chipcon_demo\cc1100+pa\newshouji\main.c
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