uart_tx.v

本实例是学习fpga的入门程序 希望大家喜欢

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:56:31 03/08/2007 
// Design Name: 
// Module Name:    uart_tx 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module uart_tx(clk, rst_n, clk_uart, txdata, txstart, txend, txd);
    input clk;
    input rst_n;
    input clk_uart;
    input [7:0] txdata;
    input txstart;
    output txend;
    output txd;


parameter CLK_FACTOR = 16 ;
parameter CLK_FACTOR_BIT = 4;
parameter START_BIT = 1 ;
parameter DATA_BIT	=8	;
parameter STOP_BIT	=1	;


`define TATOL_BIN START_BIT + DATA_BIT + STOP_BIT

wire clk_1x;
reg [CLK_FACTOR_BIT: 0] clk_cnt;
//reg [CLK_FACTOR_BIT - 1 : 0] clk_cnt;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) clk_cnt <= 0 ;
else if (clk_cnt == (CLK_FACTOR+1)) clk_cnt <= 0 ;
//else if (clk_cnt == (CLK_FACTOR-1)) clk_cnt <= 0 ;
else if (clk_uart) clk_cnt <= clk_cnt +1 ;
end
 
assign clk_1x = (clk_cnt == (CLK_FACTOR +1));  //uart clk
//assign clk_1x = (clk_cnt == (CLK_FACTOR -1)); 


reg enstart ;
reg [3:0] tx_count;
always @(posedge clk or negedge rst_n)     //uart count 
if (!rst_n) tx_count <= -1;//0
else if (tx_count==(`TATOL_BIN )) tx_count <= -1;//-1 0
else if (clk_1x && enstart) tx_count <= tx_count + 1;
reg [7:0] txdata_temp;
wire [ `TATOL_BIN-1:0 ] txbuf ={1'b1,
										txdata_temp[7:0],
										1'b0
										};
										

always @ (posedge clk)
if(txstart) 
begin 
	txdata_temp <= txdata ;
	enstart <= 1 ;
end
else if(tx_count ==(`TATOL_BIN ))  enstart <= 0;//-1

reg tx_shift ;
always @ (posedge clk or negedge rst_n)
if(!rst_n) tx_shift <= 1'b1 ;
else if (enstart && (tx_count<=(`TATOL_BIN - 1)))
		tx_shift <= txbuf[tx_count];
else if (!enstart && clk_1x)
		tx_shift <= 1'b1 ;

assign txd = tx_shift ;
assign txend = (tx_count ==(`TATOL_BIN - 1));

	
										
endmodule