sp306_led_top.stx

本实例是学习fpga的入门程序 希望大家喜欢

Release 9.1i - xst J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.39 s | Elapsed : 0.00 / 0.00 s
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "hc_led.v" in library work
Compiling verilog file "counter.v" in library work
Module <hc_led> compiled
Compiling verilog file "sp306_led_top.v" in library work
Module <counter> compiled
Module <sp306_led_top> compiled
No errors in compilation
Analysis of file <"sp306_led_top.prj"> succeeded.
 
CPU : 0.03 / 0.42 s | Elapsed : 0.00 / 0.00 s
 
--> 

Total memory usage is 112308 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)