sp306_led_top.syr

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  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : sp306_led_top.ngr
Top Level Output File Name         : sp306_led_top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 5

Cell Usage :
# BELS                             : 210
#      GND                         : 1
#      INV                         : 4
#      LUT1                        : 15
#      LUT2                        : 43
#      LUT3                        : 13
#      LUT3_D                      : 1
#      LUT4                        : 17
#      LUT4_L                      : 3
#      MUXCY                       : 52
#      MUXF5                       : 6
#      MUXF6                       : 1
#      VCC                         : 1
#      XORCY                       : 53
# FlipFlops/Latches                : 63
#      FDC                         : 16
#      FDCE                        : 9
#      FDR                         : 38
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 4
#      IBUF                        : 2
#      OBUF                        : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      48  out of   3584     1%  
 Number of Slice Flip Flops:            63  out of   7168     0%  
 Number of 4 input LUTs:                96  out of   7168     1%  
 Number of IOs:                          5
 Number of bonded IOBs:                  5  out of    141     3%  
 Number of GCLKs:                        1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 63    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------+---------------------------+-------+
Control Signal                                       | Buffer(FF name)           | Load  |
-----------------------------------------------------+---------------------------+-------+
hc_led_inst/rst_n_inv(hc_led_inst/rst_n_inv1_INV_0:O)| NONE(hc_led_inst/cnt16x_0)| 25    |
-----------------------------------------------------+---------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 6.178ns (Maximum Frequency: 161.865MHz)
   Minimum input arrival time before clock: 7.541ns
   Maximum output required time after clock: 15.286ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 6.178ns (frequency: 161.865MHz)
  Total number of paths / destination ports: 1688 / 72
-------------------------------------------------------------------------
Delay:               6.178ns (Levels of Logic = 39)
  Source:            counter_inst/cnt_0 (FF)
  Destination:       counter_inst/cnt_37 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: counter_inst/cnt_0 to counter_inst/cnt_37
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.720   0.996  counter_inst/cnt_0 (counter_inst/cnt_0)
     LUT2:I1->O            1   0.551   0.000  counter_inst/Mcount_cnt_lut<0> (N61)
     MUXCY:S->O            1   0.500   0.000  counter_inst/Mcount_cnt_cy<0> (counter_inst/Mcount_cnt_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<1> (counter_inst/Mcount_cnt_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<2> (counter_inst/Mcount_cnt_cy<2>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<3> (counter_inst/Mcount_cnt_cy<3>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<4> (counter_inst/Mcount_cnt_cy<4>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<5> (counter_inst/Mcount_cnt_cy<5>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<6> (counter_inst/Mcount_cnt_cy<6>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<7> (counter_inst/Mcount_cnt_cy<7>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<8> (counter_inst/Mcount_cnt_cy<8>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<9> (counter_inst/Mcount_cnt_cy<9>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<10> (counter_inst/Mcount_cnt_cy<10>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<11> (counter_inst/Mcount_cnt_cy<11>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<12> (counter_inst/Mcount_cnt_cy<12>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<13> (counter_inst/Mcount_cnt_cy<13>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<14> (counter_inst/Mcount_cnt_cy<14>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<15> (counter_inst/Mcount_cnt_cy<15>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<16> (counter_inst/Mcount_cnt_cy<16>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<17> (counter_inst/Mcount_cnt_cy<17>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<18> (counter_inst/Mcount_cnt_cy<18>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<19> (counter_inst/Mcount_cnt_cy<19>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<20> (counter_inst/Mcount_cnt_cy<20>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<21> (counter_inst/Mcount_cnt_cy<21>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<22> (counter_inst/Mcount_cnt_cy<22>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<23> (counter_inst/Mcount_cnt_cy<23>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<24> (counter_inst/Mcount_cnt_cy<24>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<25> (counter_inst/Mcount_cnt_cy<25>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<26> (counter_inst/Mcount_cnt_cy<26>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<27> (counter_inst/Mcount_cnt_cy<27>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<28> (counter_inst/Mcount_cnt_cy<28>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<29> (counter_inst/Mcount_cnt_cy<29>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<30> (counter_inst/Mcount_cnt_cy<30>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<31> (counter_inst/Mcount_cnt_cy<31>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<32> (counter_inst/Mcount_cnt_cy<32>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<33> (counter_inst/Mcount_cnt_cy<33>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<34> (counter_inst/Mcount_cnt_cy<34>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<35> (counter_inst/Mcount_cnt_cy<35>)
     MUXCY:CI->O           0   0.064   0.000  counter_inst/Mcount_cnt_cy<36> (counter_inst/Mcount_cnt_cy<36>)
     XORCY:CI->O           1   0.904   0.000  counter_inst/Mcount_cnt_xor<37> (Result<37>)
     FDR:D                     0.203          counter_inst/cnt_37
    ----------------------------------------
    Total                      6.178ns (5.182ns logic, 0.996ns route)
                                       (83.9% logic, 16.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 817 / 76
-------------------------------------------------------------------------
Offset:              7.541ns (Levels of Logic = 40)
  Source:            sw1 (PAD)
  Destination:       counter_inst/cnt_37 (FF)
  Destination Clock: clk rising

  Data Path: sw1 to counter_inst/cnt_37
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            39   0.821   1.893  sw1_IBUF (sw1_IBUF)
     INV:I->O              1   0.551   0.801  sw11_INV_0 (N51)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<0> (counter_inst/Mcount_cnt_cy<0>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<1> (counter_inst/Mcount_cnt_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<2> (counter_inst/Mcount_cnt_cy<2>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<3> (counter_inst/Mcount_cnt_cy<3>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<4> (counter_inst/Mcount_cnt_cy<4>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<5> (counter_inst/Mcount_cnt_cy<5>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<6> (counter_inst/Mcount_cnt_cy<6>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<7> (counter_inst/Mcount_cnt_cy<7>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<8> (counter_inst/Mcount_cnt_cy<8>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<9> (counter_inst/Mcount_cnt_cy<9>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<10> (counter_inst/Mcount_cnt_cy<10>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<11> (counter_inst/Mcount_cnt_cy<11>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<12> (counter_inst/Mcount_cnt_cy<12>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<13> (counter_inst/Mcount_cnt_cy<13>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<14> (counter_inst/Mcount_cnt_cy<14>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<15> (counter_inst/Mcount_cnt_cy<15>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<16> (counter_inst/Mcount_cnt_cy<16>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<17> (counter_inst/Mcount_cnt_cy<17>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<18> (counter_inst/Mcount_cnt_cy<18>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<19> (counter_inst/Mcount_cnt_cy<19>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<20> (counter_inst/Mcount_cnt_cy<20>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<21> (counter_inst/Mcount_cnt_cy<21>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<22> (counter_inst/Mcount_cnt_cy<22>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<23> (counter_inst/Mcount_cnt_cy<23>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<24> (counter_inst/Mcount_cnt_cy<24>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<25> (counter_inst/Mcount_cnt_cy<25>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<26> (counter_inst/Mcount_cnt_cy<26>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<27> (counter_inst/Mcount_cnt_cy<27>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<28> (counter_inst/Mcount_cnt_cy<28>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<29> (counter_inst/Mcount_cnt_cy<29>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<30> (counter_inst/Mcount_cnt_cy<30>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<31> (counter_inst/Mcount_cnt_cy<31>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<32> (counter_inst/Mcount_cnt_cy<32>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<33> (counter_inst/Mcount_cnt_cy<33>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<34> (counter_inst/Mcount_cnt_cy<34>)
     MUXCY:CI->O           1   0.064   0.000  counter_inst/Mcount_cnt_cy<35> (counter_inst/Mcount_cnt_cy<35>)
     MUXCY:CI->O           0   0.064   0.000  counter_inst/Mcount_cnt_cy<36> (counter_inst/Mcount_cnt_cy<36>)
     XORCY:CI->O           1   0.904   0.000  counter_inst/Mcount_cnt_xor<37> (Result<37>)
     FDR:D                     0.203          counter_inst/cnt_37
    ----------------------------------------
    Total                      7.541ns (4.847ns logic, 2.694ns route)
                                       (64.3% logic, 35.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 210 / 2
-------------------------------------------------------------------------
Offset:              15.286ns (Levels of Logic = 8)
  Source:            hc_led_inst/en_temp_0 (FF)
  Destination:       hc_si (PAD)
  Source Clock:      clk rising

  Data Path: hc_led_inst/en_temp_0 to hc_si
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            11   0.720   1.483  hc_led_inst/en_temp_0 (hc_led_inst/en_temp_0)
     LUT3:I0->O            1   0.551   0.000  hc_led_inst/Mmux_hex_temp_33 (N8)
     MUXF5:I1->O           7   0.360   1.405  hc_led_inst/Mmux_hex_temp_2_f5_2 (hc_led_inst/hex_temp<3>)
     LUT4:I0->O            1   0.551   1.140  hc_led_inst/Mrom_led_d31 (hc_led_inst/Mrom_led_d2)
     LUT2:I0->O            1   0.551   0.000  hc_led_inst/Mmux_hc_si_9 (N310)
     MUXF5:I0->O           1   0.360   0.000  hc_led_inst/Mmux_hc_si_7_f5 (hc_led_inst/Mmux_hc_si_7_f5)
     MUXF6:I1->O           1   0.342   0.827  hc_led_inst/Mmux_hc_si_6_f6 (hc_led_inst/Mmux_hc_si_6_f6)
     LUT4:I3->O            1   0.551   0.801  hc_led_inst/cnt_tx<4> (hc_si_OBUF)
     OBUF:I->O                 5.644          hc_si_OBUF (hc_si)
    ----------------------------------------
    Total                     15.286ns (9.630ns logic, 5.656ns route)
                                       (63.0% logic, 37.0% route)

=========================================================================
CPU : 7.31 / 7.78 s | Elapsed : 7.00 / 8.00 s
 
--> 

Total memory usage is 144768 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)