hc_led.v

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:10:50 03/04/2007 
// Design Name: 
// Module Name:    hc_led 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module hc_led(clk, rst_n, led, dot, data_value, hc_cp, hc_si);
    input clk;
    input rst_n;
    input [3:0] led;
    input [3:0] dot;
    input [15:0] data_value;
    output reg hc_cp;
    output hc_si;


reg [15:0] cnt16x;
//reg [7:0] cnt16x;

always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) cnt16x <= 0;
else cnt16x<=cnt16x+1'b1;
end

reg [3:0] led_en;
reg [6:0] led_d;
reg hc_dot;
wire [0:15] hc_data =
				{
				led[3:0],
				led_en[3:0],
				led_d[6:2],
				hc_dot,
				led_d[1:0]};

reg [1:0] en_temp;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) en_temp <= 2'b0;
else if(cnt16x==16'b1111111111111111)
//else if(cnt16x==8'b11111111)
			en_temp <= en_temp +1'b1;
end

always @ ( * )
begin
	case (en_temp)
	2'b00: led_en <= 4'b1110;
	2'b01: led_en <= 4'b1101;
	2'b10: led_en <= 4'b1011;
	2'b11: led_en <= 4'b0111;
	default : led_en <= 4'b1110;
	endcase
end

always @ ( * )
begin
	case (en_temp)
	2'b00 : hc_dot <=dot [0];
	2'b01 : hc_dot <=dot [1];
	2'b10 : hc_dot <=dot [2];
	2'b11 : hc_dot <=dot [3];
	default : hc_dot <= 1'b0;
	endcase
end

reg [3:0] hex_temp;
always @ ( * )
begin
	case (en_temp)
	2'b00 : hex_temp <= data_value [3:0] ;
	2'b01 : hex_temp <= data_value [7:4] ;
	2'b10 : hex_temp <= data_value [11:8] ;
	2'b11 : hex_temp <= data_value [15:12] ;
	//default : hex_temp <= 4'b0 ;
	endcase
end

always @ ( * )
begin
	case (hex_temp)
		   4'h1  : led_d = 7'b0010_100;	//1          
	      4'h2  : led_d = 7'b1011_011;	//2   
	      4'h3  : led_d = 7'b1011_110;	//3   
	      4'h4  : led_d = 7'b0111_100;	//4   
	      4'h5  : led_d = 7'b1101_110;	//5   
	      4'h6  : led_d = 7'b1101_111;	//6   
	      4'h7  : led_d = 7'b1010_100;	//7   
	      4'h8  : led_d = 7'b1111_111;	//8   
	      4'h9  : led_d = 7'b1111_100;	//9   
	      4'hA  : led_d = 7'b1111_101;	//A   
	      4'hB  : led_d = 7'b0101_111;	//b   
	      4'hC  : led_d = 7'b1100_011;	//C   
	      4'hD  : led_d = 7'b0011_111;	//d   
	      4'hE  : led_d = 7'b1101_011;	//E   
	      4'hF  : led_d = 7'b1101_001;	//F   
	    default : led_d = 7'b1110_111;	//0  
	
	endcase
end 

reg [5:0] cnt_tx;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) cnt_tx <= 6'b0;
//else if (cnt16x==16'b1111111111111111)
else if ((cnt16x[15])) cnt_tx <= 6'b0;
else if((cnt_tx <=6'd32)&&(!cnt16x[15]))
	cnt_tx <= cnt_tx +1'b1;
end


always @ (posedge clk or negedge rst_n)
begin
if (!rst_n) begin 
		hc_cp <= 1'b0;
	
				end
else if ((cnt16x[15])) hc_cp <= 1'b0;
else if ((cnt_tx <6'd32)&&(!cnt16x[15])) 
		begin hc_cp <= !hc_cp;
		end 
 

end

assign hc_si= hc_data[cnt_tx[4:1]];
endmodule