freque.par

本实例是学习fpga的入门程序 希望大家喜欢

Release 9.1i par J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

BABY::  Tue May 05 19:51:10 2009

par -w -intstyle ise -ol std -t 1 freque_map.ncd freque.ncd freque.pcf 


Constraints file: freque.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment D:\Xilinx9.1.
   "freque" is an NCD, version 3.1, device xc3s400, package pq208, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.39 2006-10-19".


Device Utilization Summary:

   Number of BUFGMUXs                        3 out of 8      37%
   Number of DCMs                            1 out of 4      25%
   Number of External IOBs                   5 out of 141     3%
      Number of LOCed IOBs                   5 out of 5     100%

   Number of Slices                         75 out of 3584    2%
      Number of SLICEMs                      2 out of 1792    1%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 

Starting initial Timing Analysis.  REAL time: 2 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9898c3) REAL time: 2 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.2

Phase 4.2 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.8
....
.
....
.
.
.
Phase 5.8 (Checksum:9996d8) REAL time: 5 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 5 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 5 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 5 secs 

REAL time consumed by placer: 5 secs 
CPU  time consumed by placer: 5 secs 
Writing design to file freque.ncd


Total REAL time to Placer completion: 6 secs 
Total CPU time to Placer completion: 5 secs 

Starting Router

Phase 1: 474 unrouted;       REAL time: 6 secs 

Phase 2: 417 unrouted;       REAL time: 6 secs 

Phase 3: 96 unrouted;       REAL time: 6 secs 

Phase 4: 96 unrouted; (0)      REAL time: 6 secs 

Phase 5: 96 unrouted; (0)      REAL time: 6 secs 

Phase 6: 96 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 7 secs 

Phase 8: 0 unrouted; (0)      REAL time: 7 secs 


Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 6 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           CLK2X_OUT |      BUFGMUX3| No   |   26 |  0.040     |  1.073      |
+---------------------+--------------+------+------+------------+-------------+
|data_value_cmp_eq000 |              |      |      |            |             |
|                   0 |      BUFGMUX7| No   |   10 |  0.019     |  1.033      |
+---------------------+--------------+------+------+------------+-------------+
|            CLK0_OUT |      BUFGMUX2| No   |   18 |  0.001     |  1.015      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.028
   The MAXIMUM PIN DELAY IS:                               3.932
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.604

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         245         183          35           9           0           0

Timing Score: 0

Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  TS_clk200hztop_CLK2X_BUF = PERIOD TIMEGRP | SETUP   |     1.491ns|     8.509ns|       0|           0
   "clk200hztop_CLK2X_BUF" TS_CLK / 2       | HOLD    |     0.822ns|            |       0|           0
     HIGH 50%                               |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_clk200hztop_CLK0_BUF = PERIOD TIMEGRP  | SETUP   |    13.234ns|     6.766ns|       0|           0
  "clk200hztop_CLK0_BUF" TS_CLK HIGH        | HOLD    |     1.056ns|            |       0|           0
    50%                                     |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_CLK = PERIOD TIMEGRP "CLK" 20 ns HIGH  | N/A     |         N/A|         N/A|     N/A|         N/A
  50%                                       |         |            |            |        |            
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  137 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file freque.ncd



PAR done!