freque.syr

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 1-of-4 decoder                                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2146 - In block <freque>, Counter <display_cnt> <hc_ledtop/cnt16x> are equivalent, XST will keep only <display_cnt>.
WARNING:Xst:2677 - Node <fre_count_0> of sequential type is unconnected in block <freque>.
WARNING:Xst:2677 - Node <fre_count_1> of sequential type is unconnected in block <freque>.
WARNING:Xst:2677 - Node <fre_count_2> of sequential type is unconnected in block <freque>.
WARNING:Xst:2677 - Node <fre_count_3> of sequential type is unconnected in block <freque>.
WARNING:Xst:2677 - Node <data_value_0> of sequential type is unconnected in block <freque>.
WARNING:Xst:2677 - Node <data_value_1> of sequential type is unconnected in block <freque>.
WARNING:Xst:2677 - Node <data_value_2> of sequential type is unconnected in block <freque>.
WARNING:Xst:2677 - Node <data_value_3> of sequential type is unconnected in block <freque>.

Optimizing unit <freque> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block freque, actual ratio is 2.
FlipFlop periode0 has been replicated 1 time(s)
INFO:Xst:1843 - HDL ADVISOR - FlipFlop periode0 connected to a primary input has been replicated

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 78
 Flip-Flops                                            : 78

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : freque.ngr
Top Level Output File Name         : freque
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 5

Cell Usage :
# BELS                             : 213
#      GND                         : 1
#      INV                         : 5
#      LUT1                        : 23
#      LUT2                        : 6
#      LUT3                        : 43
#      LUT4                        : 25
#      MUXCY                       : 53
#      MUXF5                       : 8
#      MUXF6                       : 2
#      MUXF7                       : 1
#      VCC                         : 1
#      XORCY                       : 45
# FlipFlops/Latches                : 98
#      FDC                         : 49
#      FDCE                        : 29
#      LD                          : 20
# Clock Buffers                    : 4
#      BUFG                        : 4
# IO Buffers                       : 5
#      IBUF                        : 2
#      IBUFG                       : 1
#      OBUF                        : 2
# DCMs                             : 1
#      DCM                         : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      74  out of   3584     2%  
 Number of Slice Flip Flops:            98  out of   7168     1%  
 Number of 4 input LUTs:               102  out of   7168     1%  
 Number of IOs:                          5
 Number of bonded IOBs:                  5  out of    141     3%  
 Number of GCLKs:                        4  out of      8    50%  
 Number of DCMs:                         1  out of      4    25%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------------------+---------------------------+-------+
Clock Signal                                   | Clock buffer(FF name)     | Load  |
-----------------------------------------------+---------------------------+-------+
CLK                                            | clk200hztop/DCM_INST:CLK2X| 47    |
CLK                                            | clk200hztop/DCM_INST:CLK0 | 31    |
data_value_cmp_eq00001(data_value_cmp_eq0000:O)| BUFG(*)(data_value_14)    | 20    |
-----------------------------------------------+---------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
RST_N_inv(RST_N_inv1_INV_0:O)      | NONE(fre_temp_6)       | 78    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 14.482ns (Maximum Frequency: 69.051MHz)
   Minimum input arrival time before clock: 1.901ns
   Maximum output required time after clock: 14.224ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 14.482ns (frequency: 69.051MHz)
  Total number of paths / destination ports: 1850 / 105
-------------------------------------------------------------------------
Delay:               7.241ns (Levels of Logic = 10)
  Source:            fre_temp_1 (FF)
  Destination:       fre_count_4 (FF)
  Source Clock:      CLK rising 2.0X
  Destination Clock: CLK rising 2.0X

  Data Path: fre_temp_1 to fre_count_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.720   1.216  fre_temp_1 (fre_temp_1)
     LUT1:I0->O            1   0.551   0.000  Mcompar_fre_count_cmp_le0000_cy<1>_rt (Mcompar_fre_count_cmp_le0000_cy<1>_rt)
     MUXCY:S->O            1   0.500   0.000  Mcompar_fre_count_cmp_le0000_cy<1> (Mcompar_fre_count_cmp_le0000_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_fre_count_cmp_le0000_cy<2> (Mcompar_fre_count_cmp_le0000_cy<2>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_fre_count_cmp_le0000_cy<3> (Mcompar_fre_count_cmp_le0000_cy<3>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_fre_count_cmp_le0000_cy<4> (Mcompar_fre_count_cmp_le0000_cy<4>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_fre_count_cmp_le0000_cy<5> (Mcompar_fre_count_cmp_le0000_cy<5>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_fre_count_cmp_le0000_cy<6> (Mcompar_fre_count_cmp_le0000_cy<6>)
     MUXCY:CI->O           1   0.064   0.000  Mcompar_fre_count_cmp_le0000_cy<7> (Mcompar_fre_count_cmp_le0000_cy<7>)
     MUXCY:CI->O           1   0.303   0.869  Mcompar_fre_count_cmp_le0000_cy<8> (fre_count_cmp_le0000)
     LUT3:I2->O           20   0.551   1.545  fre_count_not00011 (fre_count_not0001)
     FDCE:CE                   0.602          fre_count_4
    ----------------------------------------
    Total                      7.241ns (3.611ns logic, 3.630ns route)
                                       (49.9% logic, 50.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              1.901ns (Levels of Logic = 1)
  Source:            FREQUECEIN (PAD)
  Destination:       periode0 (FF)
  Destination Clock: CLK rising 2.0X

  Data Path: FREQUECEIN to periode0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.821   0.877  FREQUECEIN_IBUF (FREQUECEIN_IBUF)
     FDC:D                     0.203          periode0
    ----------------------------------------
    Total                      1.901ns (1.024ns logic, 0.877ns route)
                                       (53.9% logic, 46.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 104 / 2
-------------------------------------------------------------------------
Offset:              14.224ns (Levels of Logic = 8)
  Source:            hc_ledtop/en_temp_0 (FF)
  Destination:       HC_SI (PAD)
  Source Clock:      CLK rising

  Data Path: hc_ledtop/en_temp_0 to HC_SI
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            12   0.720   1.457  hc_ledtop/en_temp_0 (hc_ledtop/en_temp_0)
     LUT3:I0->O            1   0.551   0.000  hc_ledtop/Mmux_hex_temp_33 (N82)
     MUXF5:I1->O           7   0.360   1.405  hc_ledtop/Mmux_hex_temp_2_f5_2 (hc_ledtop/hex_temp<3>)
     LUT4:I0->O            1   0.551   1.140  hc_ledtop/Mrom_led_d31 (hc_ledtop/Mrom_led_d2)
     LUT2:I0->O            1   0.551   0.000  hc_ledtop/Mmux_hc_si_6 (N210)
     MUXF5:I0->O           1   0.360   0.000  hc_ledtop/Mmux_hc_si_4_f5 (hc_ledtop/Mmux_hc_si_4_f5)
     MUXF6:I1->O           1   0.342   0.000  hc_ledtop/Mmux_hc_si_3_f6 (hc_ledtop/Mmux_hc_si_3_f6)
     MUXF7:I1->O           1   0.342   0.801  hc_ledtop/Mmux_hc_si_2_f7 (HC_SI_OBUF)
     OBUF:I->O                 5.644          HC_SI_OBUF (HC_SI)
    ----------------------------------------
    Total                     14.224ns (9.421ns logic, 4.803ns route)
                                       (66.2% logic, 33.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'data_value_cmp_eq00001'
  Total number of paths / destination ports: 116 / 1
-------------------------------------------------------------------------
Offset:              13.676ns (Levels of Logic = 8)
  Source:            data_value_11 (LATCH)
  Destination:       HC_SI (PAD)
  Source Clock:      data_value_cmp_eq00001 falling

  Data Path: data_value_11 to HC_SI
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q               1   0.633   0.996  data_value_11 (data_value_11)
     LUT3:I1->O            1   0.551   0.000  hc_ledtop/Mmux_hex_temp_43 (N91)
     MUXF5:I0->O           7   0.360   1.405  hc_ledtop/Mmux_hex_temp_2_f5_2 (hc_ledtop/hex_temp<3>)
     LUT4:I0->O            1   0.551   1.140  hc_ledtop/Mrom_led_d31 (hc_ledtop/Mrom_led_d2)
     LUT2:I0->O            1   0.551   0.000  hc_ledtop/Mmux_hc_si_6 (N210)
     MUXF5:I0->O           1   0.360   0.000  hc_ledtop/Mmux_hc_si_4_f5 (hc_ledtop/Mmux_hc_si_4_f5)
     MUXF6:I1->O           1   0.342   0.000  hc_ledtop/Mmux_hc_si_3_f6 (hc_ledtop/Mmux_hc_si_3_f6)
     MUXF7:I1->O           1   0.342   0.801  hc_ledtop/Mmux_hc_si_2_f7 (HC_SI_OBUF)
     OBUF:I->O                 5.644          HC_SI_OBUF (HC_SI)
    ----------------------------------------
    Total                     13.676ns (9.334ns logic, 4.342ns route)
                                       (68.3% logic, 31.7% route)

=========================================================================
CPU : 8.38 / 9.33 s | Elapsed : 8.00 / 9.00 s
 
--> 

Total memory usage is 145792 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   17 (   0 filtered)
Number of infos    :    2 (   0 filtered)