freque.twr

本实例是学习fpga的入门程序 希望大家喜欢

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Release 9.1i Trace 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

D:\Xilinx9.1\bin\nt\trce.exe -ise E:/fpgaproject/frequence/frequence.ise
-intstyle ise -e 3 -s 4 -xml freque freque.ncd -o freque.twr freque.pcf -ucf
freque.ucf

Design file:              freque.ncd
Physical constraint file: freque.pcf
Device,package,speed:     xc3s400,pq208,-4 (PRODUCTION 1.39 2006-10-19)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_CLK = PERIOD TIMEGRP "CLK" 20 ns HIGH 50%;

 0 items analyzed, 0 timing errors detected.
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================================================================================
Timing constraint: TS_clk200hztop_CLK0_BUF = PERIOD TIMEGRP "clk200hztop_CLK0_BUF" TS_CLK HIGH
        50%;

 361 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   6.766ns.
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================================================================================
Timing constraint: TS_clk200hztop_CLK2X_BUF = PERIOD TIMEGRP "clk200hztop_CLK2X_BUF" TS_CLK / 2
        HIGH 50%;

 1489 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   8.509ns.
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All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    8.509|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 1850 paths, 0 nets, and 296 connections

Design statistics:
   Minimum period:   8.509ns   (Maximum frequency: 117.523MHz)


Analysis completed Tue May 05 19:51:22 2009
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Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 99 MB