dpram_0it.tdf

在quartus开发环境下

--altdpram DEVICE_FAMILY="Cyclone II" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=8 WIDTHAD=3 data inclock outclock outclocken q rdaddress wraddress wren CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" LOW_POWER_MODE="AUTO"
--VERSION_BEGIN 7.0 cbx_altdpram 2006:11:03:15:22:16:SJ cbx_altsyncram 2007:01:25:14:36:16:SJ cbx_cycloneii 2006:09:29:19:03:26:SJ cbx_lpm_add_sub 2006:10:10:22:03:24:SJ cbx_lpm_compare 2006:04:25:14:54:12:SJ cbx_lpm_decode 2006:04:25:15:10:18:SJ cbx_lpm_mux 2006:04:25:15:10:08:SJ cbx_mgl 2006:10:27:16:08:48:SJ cbx_stratix 2006:09:18:10:47:42:SJ cbx_stratixii 2006:10:13:14:01:30:SJ cbx_stratixiii 2006:10:19:19:28:28:SJ cbx_util_mgl 2006:11:03:10:32:30:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
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--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.


FUNCTION altsyncram_urj1 (address_a[2..0], address_b[2..0], clock0, clock1, clocken1, data_a[7..0], wren_a)
RETURNS ( q_b[7..0]);

--synthesis_resources = M4K 1 
SUBDESIGN dpram_0it
( 
	data[7..0]	:	input;
	inclock	:	input;
	outclock	:	input;
	outclocken	:	input;
	q[7..0]	:	output;
	rdaddress[2..0]	:	input;
	wraddress[2..0]	:	input;
	wren	:	input;
) 
VARIABLE 
	altsyncram2 : altsyncram_urj1;

BEGIN 
	altsyncram2.address_a[] = wraddress[];
	altsyncram2.address_b[] = rdaddress[];
	altsyncram2.clock0 = inclock;
	altsyncram2.clock1 = outclock;
	altsyncram2.clocken1 = outclocken;
	altsyncram2.data_a[] = data[];
	altsyncram2.wren_a = wren;
	q[] = altsyncram2.q_b[];
END;
--VALID FILE