fifo_1.hier_info

在quartus开发环境下

|FIFO_1
full <= lpm_fifo0:inst.full
wr => lpm_fifo0:inst.wrreq
rd => lpm_fifo0:inst.rdreq
clk => lpm_fifo0:inst.clock
din[0] => lpm_fifo0:inst.data[0]
din[1] => lpm_fifo0:inst.data[1]
din[2] => lpm_fifo0:inst.data[2]
din[3] => lpm_fifo0:inst.data[3]
din[4] => lpm_fifo0:inst.data[4]
din[5] => lpm_fifo0:inst.data[5]
din[6] => lpm_fifo0:inst.data[6]
din[7] => lpm_fifo0:inst.data[7]
empty <= lpm_fifo0:inst.empty
dout[0] <= lpm_fifo0:inst.q[0]
dout[1] <= lpm_fifo0:inst.q[1]
dout[2] <= lpm_fifo0:inst.q[2]
dout[3] <= lpm_fifo0:inst.q[3]
dout[4] <= lpm_fifo0:inst.q[4]
dout[5] <= lpm_fifo0:inst.q[5]
dout[6] <= lpm_fifo0:inst.q[6]
dout[7] <= lpm_fifo0:inst.q[7]
usdw[0] <= lpm_fifo0:inst.usedw[0]
usdw[1] <= lpm_fifo0:inst.usedw[1]
usdw[2] <= lpm_fifo0:inst.usedw[2]


|FIFO_1|lpm_fifo0:inst
clock => scfifo:scfifo_component.clock
data[0] => scfifo:scfifo_component.data[0]
data[1] => scfifo:scfifo_component.data[1]
data[2] => scfifo:scfifo_component.data[2]
data[3] => scfifo:scfifo_component.data[3]
data[4] => scfifo:scfifo_component.data[4]
data[5] => scfifo:scfifo_component.data[5]
data[6] => scfifo:scfifo_component.data[6]
data[7] => scfifo:scfifo_component.data[7]
rdreq => scfifo:scfifo_component.rdreq
wrreq => scfifo:scfifo_component.wrreq
empty <= scfifo:scfifo_component.empty
full <= scfifo:scfifo_component.full
q[0] <= scfifo:scfifo_component.q[0]
q[1] <= scfifo:scfifo_component.q[1]
q[2] <= scfifo:scfifo_component.q[2]
q[3] <= scfifo:scfifo_component.q[3]
q[4] <= scfifo:scfifo_component.q[4]
q[5] <= scfifo:scfifo_component.q[5]
q[6] <= scfifo:scfifo_component.q[6]
q[7] <= scfifo:scfifo_component.q[7]
usedw[0] <= scfifo:scfifo_component.usedw[0]
usedw[1] <= scfifo:scfifo_component.usedw[1]
usedw[2] <= scfifo:scfifo_component.usedw[2]


|FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component
data[0] => scfifo_4uv:auto_generated.data[0]
data[1] => scfifo_4uv:auto_generated.data[1]
data[2] => scfifo_4uv:auto_generated.data[2]
data[3] => scfifo_4uv:auto_generated.data[3]
data[4] => scfifo_4uv:auto_generated.data[4]
data[5] => scfifo_4uv:auto_generated.data[5]
data[6] => scfifo_4uv:auto_generated.data[6]
data[7] => scfifo_4uv:auto_generated.data[7]
q[0] <= scfifo_4uv:auto_generated.q[0]
q[1] <= scfifo_4uv:auto_generated.q[1]
q[2] <= scfifo_4uv:auto_generated.q[2]
q[3] <= scfifo_4uv:auto_generated.q[3]
q[4] <= scfifo_4uv:auto_generated.q[4]
q[5] <= scfifo_4uv:auto_generated.q[5]
q[6] <= scfifo_4uv:auto_generated.q[6]
q[7] <= scfifo_4uv:auto_generated.q[7]
wrreq => scfifo_4uv:auto_generated.wrreq
rdreq => scfifo_4uv:auto_generated.rdreq
clock => scfifo_4uv:auto_generated.clock
aclr => ~NO_FANOUT~
sclr => ~NO_FANOUT~
empty <= scfifo_4uv:auto_generated.empty
full <= scfifo_4uv:auto_generated.full
almost_full <= <GND>
almost_empty <= <GND>
usedw[0] <= scfifo_4uv:auto_generated.usedw[0]
usedw[1] <= scfifo_4uv:auto_generated.usedw[1]
usedw[2] <= scfifo_4uv:auto_generated.usedw[2]


|FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated
clock => a_dpfifo_b401:dpfifo.clock
data[0] => a_dpfifo_b401:dpfifo.data[0]
data[1] => a_dpfifo_b401:dpfifo.data[1]
data[2] => a_dpfifo_b401:dpfifo.data[2]
data[3] => a_dpfifo_b401:dpfifo.data[3]
data[4] => a_dpfifo_b401:dpfifo.data[4]
data[5] => a_dpfifo_b401:dpfifo.data[5]
data[6] => a_dpfifo_b401:dpfifo.data[6]
data[7] => a_dpfifo_b401:dpfifo.data[7]
empty <= a_dpfifo_b401:dpfifo.empty
full <= a_dpfifo_b401:dpfifo.full
q[0] <= a_dpfifo_b401:dpfifo.q[0]
q[1] <= a_dpfifo_b401:dpfifo.q[1]
q[2] <= a_dpfifo_b401:dpfifo.q[2]
q[3] <= a_dpfifo_b401:dpfifo.q[3]
q[4] <= a_dpfifo_b401:dpfifo.q[4]
q[5] <= a_dpfifo_b401:dpfifo.q[5]
q[6] <= a_dpfifo_b401:dpfifo.q[6]
q[7] <= a_dpfifo_b401:dpfifo.q[7]
rdreq => a_dpfifo_b401:dpfifo.rreq
usedw[0] <= a_dpfifo_b401:dpfifo.usedw[0]
usedw[1] <= a_dpfifo_b401:dpfifo.usedw[1]
usedw[2] <= a_dpfifo_b401:dpfifo.usedw[2]
wrreq => a_dpfifo_b401:dpfifo.wreq


|FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo
clock => a_fefifo_m4f:fifo_state.clock
clock => dpram_0it:FIFOram.inclock
clock => dpram_0it:FIFOram.outclock
clock => cntr_cjb:rd_ptr_count.clock
clock => cntr_cjb:wr_ptr.clock
data[0] => dpram_0it:FIFOram.data[0]
data[1] => dpram_0it:FIFOram.data[1]
data[2] => dpram_0it:FIFOram.data[2]
data[3] => dpram_0it:FIFOram.data[3]
data[4] => dpram_0it:FIFOram.data[4]
data[5] => dpram_0it:FIFOram.data[5]
data[6] => dpram_0it:FIFOram.data[6]
data[7] => dpram_0it:FIFOram.data[7]
empty <= a_fefifo_m4f:fifo_state.empty
full <= a_fefifo_m4f:fifo_state.full
q[0] <= dpram_0it:FIFOram.q[0]
q[1] <= dpram_0it:FIFOram.q[1]
q[2] <= dpram_0it:FIFOram.q[2]
q[3] <= dpram_0it:FIFOram.q[3]
q[4] <= dpram_0it:FIFOram.q[4]
q[5] <= dpram_0it:FIFOram.q[5]
q[6] <= dpram_0it:FIFOram.q[6]
q[7] <= dpram_0it:FIFOram.q[7]
rreq => a_fefifo_m4f:fifo_state.rreq
rreq => valid_rreq.IN0
sclr => a_fefifo_m4f:fifo_state.sclr
sclr => cntr_cjb:rd_ptr_count.sclr
sclr => cntr_cjb:wr_ptr.sclr
usedw[0] <= a_fefifo_m4f:fifo_state.usedw_out[0]
usedw[1] <= a_fefifo_m4f:fifo_state.usedw_out[1]
usedw[2] <= a_fefifo_m4f:fifo_state.usedw_out[2]
wreq => a_fefifo_m4f:fifo_state.wreq
wreq => valid_wreq.IN0


|FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state
aclr => cntr_oj7:count_usedw.aclr
clock => cntr_oj7:count_usedw.clock
clock => b_full.CLK
clock => b_non_empty.CLK
full <= b_full.DB_MAX_OUTPUT_PORT_TYPE
rreq => valid_rreq.IN0
sclr => cntr_oj7:count_usedw.sclr
usedw_out[0] <= usedw[0].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[1] <= usedw[1].DB_MAX_OUTPUT_PORT_TYPE
usedw_out[2] <= usedw[2].DB_MAX_OUTPUT_PORT_TYPE
wreq => valid_wreq.IN0


|FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw
aclr => counter_reg_bit1a[2].ACLR
aclr => counter_reg_bit1a[1].ACLR
aclr => counter_reg_bit1a[0].ACLR
clock => counter_reg_bit1a[2].CLK
clock => counter_reg_bit1a[1].CLK
clock => counter_reg_bit1a[0].CLK
q[0] <= counter_reg_bit1a[0].REGOUT
q[1] <= counter_reg_bit1a[1].REGOUT
q[2] <= counter_reg_bit1a[2].REGOUT
updown => counter_comb_bita0.DATAB
updown => counter_comb_bita1.DATAB
updown => counter_comb_bita2.DATAB


|FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram
data[0] => altsyncram_urj1:altsyncram2.data_a[0]
data[1] => altsyncram_urj1:altsyncram2.data_a[1]
data[2] => altsyncram_urj1:altsyncram2.data_a[2]
data[3] => altsyncram_urj1:altsyncram2.data_a[3]
data[4] => altsyncram_urj1:altsyncram2.data_a[4]
data[5] => altsyncram_urj1:altsyncram2.data_a[5]
data[6] => altsyncram_urj1:altsyncram2.data_a[6]
data[7] => altsyncram_urj1:altsyncram2.data_a[7]
inclock => altsyncram_urj1:altsyncram2.clock0
outclock => altsyncram_urj1:altsyncram2.clock1
outclocken => altsyncram_urj1:altsyncram2.clocken1
q[0] <= altsyncram_urj1:altsyncram2.q_b[0]
q[1] <= altsyncram_urj1:altsyncram2.q_b[1]
q[2] <= altsyncram_urj1:altsyncram2.q_b[2]
q[3] <= altsyncram_urj1:altsyncram2.q_b[3]
q[4] <= altsyncram_urj1:altsyncram2.q_b[4]
q[5] <= altsyncram_urj1:altsyncram2.q_b[5]
q[6] <= altsyncram_urj1:altsyncram2.q_b[6]
q[7] <= altsyncram_urj1:altsyncram2.q_b[7]
rdaddress[0] => altsyncram_urj1:altsyncram2.address_b[0]
rdaddress[1] => altsyncram_urj1:altsyncram2.address_b[1]
rdaddress[2] => altsyncram_urj1:altsyncram2.address_b[2]
wraddress[0] => altsyncram_urj1:altsyncram2.address_a[0]
wraddress[1] => altsyncram_urj1:altsyncram2.address_a[1]
wraddress[2] => altsyncram_urj1:altsyncram2.address_a[2]
wren => altsyncram_urj1:altsyncram2.wren_a


|FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram|altsyncram_urj1:altsyncram2
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
clock0 => ram_block3a0.CLK0
clock0 => ram_block3a1.CLK0
clock0 => ram_block3a2.CLK0
clock0 => ram_block3a3.CLK0
clock0 => ram_block3a4.CLK0
clock0 => ram_block3a5.CLK0
clock0 => ram_block3a6.CLK0
clock0 => ram_block3a7.CLK0
clock1 => ram_block3a0.CLK1
clock1 => ram_block3a1.CLK1
clock1 => ram_block3a2.CLK1
clock1 => ram_block3a3.CLK1
clock1 => ram_block3a4.CLK1
clock1 => ram_block3a5.CLK1
clock1 => ram_block3a6.CLK1
clock1 => ram_block3a7.CLK1
clocken1 => ram_block3a0.ENA1
clocken1 => ram_block3a1.ENA1
clocken1 => ram_block3a2.ENA1
clocken1 => ram_block3a3.ENA1
clocken1 => ram_block3a4.ENA1
clocken1 => ram_block3a5.ENA1
clocken1 => ram_block3a6.ENA1
clocken1 => ram_block3a7.ENA1
data_a[0] => ram_block3a0.PORTADATAIN
data_a[1] => ram_block3a1.PORTADATAIN
data_a[2] => ram_block3a2.PORTADATAIN
data_a[3] => ram_block3a3.PORTADATAIN
data_a[4] => ram_block3a4.PORTADATAIN
data_a[5] => ram_block3a5.PORTADATAIN
data_a[6] => ram_block3a6.PORTADATAIN
data_a[7] => ram_block3a7.PORTADATAIN
q_b[0] <= ram_block3a0.PORTBDATAOUT
q_b[1] <= ram_block3a1.PORTBDATAOUT
q_b[2] <= ram_block3a2.PORTBDATAOUT
q_b[3] <= ram_block3a3.PORTBDATAOUT
q_b[4] <= ram_block3a4.PORTBDATAOUT
q_b[5] <= ram_block3a5.PORTBDATAOUT
q_b[6] <= ram_block3a6.PORTBDATAOUT
q_b[7] <= ram_block3a7.PORTBDATAOUT
wren_a => ram_block3a0.ENA0
wren_a => ram_block3a1.ENA0
wren_a => ram_block3a2.ENA0
wren_a => ram_block3a3.ENA0
wren_a => ram_block3a4.ENA0
wren_a => ram_block3a5.ENA0
wren_a => ram_block3a6.ENA0
wren_a => ram_block3a7.ENA0


|FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count
aclr => counter_reg_bit4a[2].ACLR
aclr => counter_reg_bit4a[1].ACLR
aclr => counter_reg_bit4a[0].ACLR
clock => counter_reg_bit4a[2].CLK
clock => counter_reg_bit4a[1].CLK
clock => counter_reg_bit4a[0].CLK
q[0] <= counter_reg_bit4a[0].REGOUT
q[1] <= counter_reg_bit4a[1].REGOUT
q[2] <= counter_reg_bit4a[2].REGOUT


|FIFO_1|lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr
aclr => counter_reg_bit4a[2].ACLR
aclr => counter_reg_bit4a[1].ACLR
aclr => counter_reg_bit4a[0].ACLR
clock => counter_reg_bit4a[2].CLK
clock => counter_reg_bit4a[1].CLK
clock => counter_reg_bit4a[0].CLK
q[0] <= counter_reg_bit4a[0].REGOUT
q[1] <= counter_reg_bit4a[1].REGOUT
q[2] <= counter_reg_bit4a[2].REGOUT