fifo_1.hif

在quartus开发环境下

Version 7.0 Build 33 02/05/2007 SJ Full Version
11
807
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
scfifo
# storage
db|FIFO_1.(2).cnf
db|FIFO_1.(2).cnf
# case_insensitive
# source_file
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|scfifo.tdf
b595a49558d9be53086a660930ab77
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
8
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
3
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_sbv
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# include_file {
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
}
# end
# entity
scfifo_sbv
# storage
db|FIFO_1.(3).cnf
db|FIFO_1.(3).cnf
# case_insensitive
# source_file
db|scfifo_sbv.tdf
39f205aa37937ec23204e368fcb2abf
6
# used_port {
wrreq
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# end
# entity
a_dpfifo_3iv
# storage
db|FIFO_1.(4).cnf
db|FIFO_1.(4).cnf
# case_insensitive
# source_file
db|a_dpfifo_3iv.tdf
df4c895eedf59781ff4e83d8f86e1a7
6
# used_port {
wreq
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# end
# entity
a_fefifo_n4e
# storage
db|FIFO_1.(5).cnf
db|FIFO_1.(5).cnf
# case_insensitive
# source_file
db|a_fefifo_n4e.tdf
beda5a94e630851d29e731d4e5c2ea
6
# used_port {
wreq
-1
3
sclr
-1
3
rreq
-1
3
full
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# end
# entity
cntr_oj7
# storage
db|FIFO_1.(6).cnf
db|FIFO_1.(6).cnf
# case_insensitive
# source_file
db|cntr_oj7.tdf
89de9c6365671c7bed3e31633c82615
6
# used_port {
updown
-1
3
sclr
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state|cntr_oj7:count_usedw
}
# end
# entity
dpram_0it
# storage
db|FIFO_1.(7).cnf
db|FIFO_1.(7).cnf
# case_insensitive
# source_file
db|dpram_0it.tdf
96e5ac7d40a6b14fc14cc5ee5c61b3a5
6
# used_port {
wren
-1
3
wraddress2
-1
3
wraddress1
-1
3
wraddress0
-1
3
rdaddress2
-1
3
rdaddress1
-1
3
rdaddress0
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
outclocken
-1
3
outclock
-1
3
inclock
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram
}
# end
# entity
altsyncram_urj1
# storage
db|FIFO_1.(8).cnf
db|FIFO_1.(8).cnf
# case_insensitive
# source_file
db|altsyncram_urj1.tdf
aeb6999f6b84c15c57f5dffdf7db85b
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a7
-1
3
data_a6
-1
3
data_a5
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clock1
-1
3
clock0
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# hierarchies {
lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|dpram_0it:FIFOram|altsyncram_urj1:altsyncram2
}
# end
# entity
cntr_cjb
# storage
db|FIFO_1.(9).cnf
db|FIFO_1.(9).cnf
# case_insensitive
# source_file
db|cntr_cjb.tdf
bbfd972965a681b196c183c3975a5aee
6
# used_port {
sclr
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:rd_ptr_count
lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|cntr_cjb:wr_ptr
}
# end
# entity
FIFO_1
# storage
db|FIFO_1.(0).cnf
db|FIFO_1.(0).cnf
# case_insensitive
# source_file
FIFO_1.bdf
76e358e7ddc3ea8c2fa744eb7ae7fb9
24
# hierarchies {
|
}
# end
# entity
lpm_fifo0
# storage
db|FIFO_1.(1).cnf
db|FIFO_1.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
lpm_fifo0.vhd
75cf8d4933c6f198b57f955e7627f479
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
lpm_fifo0:inst
}
# end
# entity
scfifo
# storage
db|FIFO_1.(10).cnf
db|FIFO_1.(10).cnf
# case_insensitive
# source_file
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|scfifo.tdf
b595a49558d9be53086a660930ab77
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
lpm_width
8
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
8
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHU
3
PARAMETER_SIGNED_DEC
USR
LPM_SHOWAHEAD
OFF
PARAMETER_UNKNOWN
USR
UNDERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
OVERFLOW_CHECKING
ON
PARAMETER_UNKNOWN
USR
ALLOW_RWCYCLE_WHEN_FULL
OFF
PARAMETER_UNKNOWN
DEF
ADD_RAM_OUTPUT_REGISTER
OFF
PARAMETER_UNKNOWN
USR
ALMOST_FULL_VALUE
0
PARAMETER_UNKNOWN
DEF
ALMOST_EMPTY_VALUE
0
PARAMETER_UNKNOWN
DEF
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
scfifo_4uv
PARAMETER_UNKNOWN
USR
}
# used_port {
wrreq
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# include_file {
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_dpfifo.inc
748303753a041187a5d4113b5f62acf
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_regfifo.inc
afe6bfc54c15224ce61beaea9e71dc
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_i2fifo.inc
ca5bb76c5a51df22b24c8b01cbcc918
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_fffifo.inc
ebf62e69b8fb10b5db33a57861298d55
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|a_f2fifo.inc
9bc132bd4e9e2ef1fb9633f6a742f
e:|altera|quartus ii7.0|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
}
# hierarchies {
lpm_fifo0:inst|scfifo:scfifo_component
}
# end
# entity
scfifo_4uv
# storage
db|FIFO_1.(11).cnf
db|FIFO_1.(11).cnf
# case_insensitive
# source_file
db|scfifo_4uv.tdf
9bc7526256384d895f125e7a2b53e6a0
6
# used_port {
wrreq
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
rdreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# hierarchies {
lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated
}
# end
# entity
a_dpfifo_b401
# storage
db|FIFO_1.(12).cnf
db|FIFO_1.(12).cnf
# case_insensitive
# source_file
db|a_dpfifo_b401.tdf
c817dea43a9f0b82585f5444816e9fe
6
# used_port {
wreq
-1
3
usedw2
-1
3
usedw1
-1
3
usedw0
-1
3
sclr
-1
3
rreq
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
full
-1
3
empty
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data1
-1
3
data0
-1
3
clock
-1
3
}
# hierarchies {
lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo
}
# end
# entity
a_fefifo_m4f
# storage
db|FIFO_1.(13).cnf
db|FIFO_1.(13).cnf
# case_insensitive
# source_file
db|a_fefifo_m4f.tdf
c45c2b8ed47d6f9d6c7a2538c9a5936
6
# used_port {
wreq
-1
3
usedw_out2
-1
3
usedw_out1
-1
3
usedw_out0
-1
3
sclr
-1
3
rreq
-1
3
full
-1
3
empty
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
lpm_fifo0:inst|scfifo:scfifo_component|scfifo_4uv:auto_generated|a_dpfifo_b401:dpfifo|a_fefifo_m4f:fifo_state
}
# end
# complete