any_div.tan.qmsg

在quartus开发环境下

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register clkdiv1~_Duplicate_1 register clkdiv1~_Duplicate_1 -1.15 ns " "Info: Minimum slack time is -1.15 ns for clock \"clk\" between source register \"clkdiv1~_Duplicate_1\" and destination register \"clkdiv1~_Duplicate_1\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Shortest register register " "Info: + Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkdiv1~_Duplicate_1 1 REG LCFF_X20_Y11_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y11_N9; Fanout = 2; REG Node = 'clkdiv1~_Duplicate_1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkdiv1~_Duplicate_1 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns clkdiv1~2 2 COMB LCCOMB_X20_Y11_N8 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X20_Y11_N8; Fanout = 1; COMB Node = 'clkdiv1~2'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.323 ns" { clkdiv1~_Duplicate_1 clkdiv1~2 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns clkdiv1~_Duplicate_1 3 REG LCFF_X20_Y11_N9 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X20_Y11_N9; Fanout = 2; REG Node = 'clkdiv1~_Duplicate_1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { clkdiv1~2 clkdiv1~_Duplicate_1 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.407 ns" { clkdiv1~_Duplicate_1 clkdiv1~2 clkdiv1~_Duplicate_1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "0.407 ns" { clkdiv1~_Duplicate_1 clkdiv1~2 clkdiv1~_Duplicate_1 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "1.557 ns - Smallest register register " "Info: - Smallest register to register requirement is 1.557 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 10.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 10.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 10.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.541 ns + Smallest " "Info: + Smallest clock skew is 1.541 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.928 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.928 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.787 ns) 2.625 ns cnt1\[11\] 3 REG LCFF_X21_Y12_N23 3 " "Info: 3: + IC(0.727 ns) + CELL(0.787 ns) = 2.625 ns; Loc. = LCFF_X21_Y12_N23; Fanout = 3; REG Node = 'cnt1\[11\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.514 ns" { clk~clkctrl cnt1[11] } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.715 ns) + CELL(0.275 ns) 3.615 ns Equal0~337 4 COMB LCCOMB_X20_Y12_N8 1 " "Info: 4: + IC(0.715 ns) + CELL(0.275 ns) = 3.615 ns; Loc. = LCCOMB_X20_Y12_N8; Fanout = 1; COMB Node = 'Equal0~337'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.990 ns" { cnt1[11] Equal0~337 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.150 ns) 4.476 ns Equal0~339 5 COMB LCCOMB_X20_Y11_N12 1 " "Info: 5: + IC(0.711 ns) + CELL(0.150 ns) = 4.476 ns; Loc. = LCCOMB_X20_Y11_N12; Fanout = 1; COMB Node = 'Equal0~339'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.861 ns" { Equal0~337 Equal0~339 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.264 ns) + CELL(0.410 ns) 5.150 ns Equal0~344 6 COMB LCCOMB_X20_Y11_N18 3 " "Info: 6: + IC(0.264 ns) + CELL(0.410 ns) = 5.150 ns; Loc. = LCCOMB_X20_Y11_N18; Fanout = 3; COMB Node = 'Equal0~344'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.674 ns" { Equal0~339 Equal0~344 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.241 ns) + CELL(0.537 ns) 5.928 ns clkdiv1~_Duplicate_1 7 REG LCFF_X20_Y11_N9 2 " "Info: 7: + IC(0.241 ns) + CELL(0.537 ns) = 5.928 ns; Loc. = LCFF_X20_Y11_N9; Fanout = 2; REG Node = 'clkdiv1~_Duplicate_1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.778 ns" { Equal0~344 clkdiv1~_Duplicate_1 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.148 ns ( 53.10 % ) " "Info: Total cell delay = 3.148 ns ( 53.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.780 ns ( 46.90 % ) " "Info: Total interconnect delay = 2.780 ns ( 46.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.928 ns" { clk clk~clkctrl cnt1[11] Equal0~337 Equal0~339 Equal0~344 clkdiv1~_Duplicate_1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.928 ns" { clk clk~combout clk~clkctrl cnt1[11] Equal0~337 Equal0~339 Equal0~344 clkdiv1~_Duplicate_1 } { 0.000ns 0.000ns 0.122ns 0.727ns 0.715ns 0.711ns 0.264ns 0.241ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.275ns 0.150ns 0.410ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.387 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 4.387 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 32 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 32; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.787 ns) 2.622 ns cnt1\[2\] 3 REG LCFF_X20_Y11_N11 3 " "Info: 3: + IC(0.724 ns) + CELL(0.787 ns) = 2.622 ns; Loc. = LCFF_X20_Y11_N11; Fanout = 3; REG Node = 'cnt1\[2\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.511 ns" { clk~clkctrl cnt1[2] } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.308 ns) + CELL(0.150 ns) 3.080 ns Equal0~341 4 COMB LCCOMB_X20_Y11_N4 1 " "Info: 4: + IC(0.308 ns) + CELL(0.150 ns) = 3.080 ns; Loc. = LCCOMB_X20_Y11_N4; Fanout = 1; COMB Node = 'Equal0~341'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.458 ns" { cnt1[2] Equal0~341 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.275 ns) 3.609 ns Equal0~344 5 COMB LCCOMB_X20_Y11_N18 3 " "Info: 5: + IC(0.254 ns) + CELL(0.275 ns) = 3.609 ns; Loc. = LCCOMB_X20_Y11_N18; Fanout = 3; COMB Node = 'Equal0~344'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.529 ns" { Equal0~341 Equal0~344 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.241 ns) + CELL(0.537 ns) 4.387 ns clkdiv1~_Duplicate_1 6 REG LCFF_X20_Y11_N9 2 " "Info: 6: + IC(0.241 ns) + CELL(0.537 ns) = 4.387 ns; Loc. = LCFF_X20_Y11_N9; Fanout = 2; REG Node = 'clkdiv1~_Duplicate_1'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.778 ns" { Equal0~344 clkdiv1~_Duplicate_1 } "NODE_NAME" } } { "any_div.vhd" "" { Text "D:/my_eda/any_div/any_div.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.738 ns ( 62.41 % ) " "Info: Total cell delay = 2.738 ns ( 62.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.649 ns ( 37.59 % ) " "Info: Total interconnect delay = 1.649 ns ( 37.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.387 ns" { clk clk~clkctrl cnt1[2] Equal0~341 Equal0~344 clkdiv1~_Duplicate_1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.387 ns" { clk clk~combout clk~clkctrl cnt1[2] Equal0~341 Equal0~344 clkdiv1~_Duplicate_1 } { 0.000ns 0.000ns 0.122ns 0.724ns 0.308ns 0.254ns 0.241ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.150ns 0.275ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.928 ns" { clk clk~clkctrl cnt1[11] Equal0~337 Equal0~339 Equal0~344 clkdiv1~_Duplicate_1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "5.928 ns" { clk clk~combout clk~clkctrl cnt1[11] Equal0~337 Equal0~339 Equal0~344 clkdiv1~_Duplicate_1 } { 0.000ns 0.000ns 0.122ns 0.727ns 0.715ns 0.711ns 0.264ns 0.241ns } { 0.000ns 0.989ns 0.000ns 0.787ns 0.275ns 0.150ns 0.410ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.387 ns" { clk clk~clkctrl cnt1[2] Equal0~341 Equal0~344 clkdiv1~_Duplicate_1 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.387 ns" { clk clk~combout clk~clkctrl cnt1[2] Equal0~341 Equal0~344 clkdiv1~_Duplicate_1 } { 0.000ns 0.000ns 0.122ns 0.724ns 0.308ns 0.254ns 0.241ns } { 0.000ns 0.989n